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Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together

Comments(0)Filed under: thermal, low-power, power, low power, PSO, voltage, shutoff, MSV, AVS, IP, power-aware, CPF, DVFS, simulation, IR drop, LDO, adaptive, Dynamic power, scaling, RNM, Khan, PVT, frequency, mixed-signal, mixed signal

This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV).

My previous blogs covered some of the following topics:

1. Basics of dynamic power management
2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal SoCs
3. How to create a controlled voltage source using a Specman testbench
4. Closed-loop voltage scaling
5. Simulation of closed-loop adaptive voltage scaling
6. Error detection
7. Analog coverage metrics

Previous postings include:

Digital-Centric Mixed Signal Verification

The digital mixed-signal (DMS) methodology is based on the use of Real Number Modeling (RNM) to model analog components at the SoC level (this was introduced in the first posting in this series of blogs). With the help of RNM, users can perform verification of their analog or mixed-signal designs using discretely simulated real numbers using only the digital solver. By avoiding traditional, slower analog simulation, intensive verification of mixed-signal designs can be performed in short period of time.

To meet the verification goals, a certain amount of simulation data and data accuracy are required. For example, a detailed analysis of an RF low noise amplifier requires very high simulation accuracy, but a single RF sinusoid period might be sufficient. On the other hand, a pin connectivity check for a large digital block has an extremely low sensitivity towards accuracy, but may require a long transient simulation time to cover all sorts of events and states.

Consequently, a long full-chip simulation run using the highest level of simulation accuracy would be desirable. The limiting factor in this context is simulation performance. The only practical way around this problem is a hierarchical verification approach that uses different level of design abstractions for different verification goals.

Real number modeling is an interesting add-on to classical mixed signal verification approaches, like a Verilog and Spice mixed signal simulation, or a pure digital modeling of the analog block in the mixed signal design. The extremely high accuracy of traditional analog simulation is traded off for speed, while still preserving enough accuracy to enable the highly accurate interaction between digital and analog domains that is required for a full SoC level simulation.

The target audiences for DMS are analog, digital, and mixed-signal engineers seeking high performance mixed signal verification with the ability to:

  • Perform high volume, digital-centric nightly regressions tests to verify their mixed signal SoCs
  • Verifying top-level SoCs that have a small to moderate amount of analog in the design

RNM also opens the possibility of linkage with other advanced verification techniques such as metric-driven and assertion-based verification without the difficulty of interfacing to the analog engine or defining new semantics to deal with analog values.

Figure 1: DMS Methodology - SoC top-level simulation environment using real number models

In this series of blogs, DMSV was applied successfully to the verification of adaptive dynamic voltage and frequency scaling (DVFS). Key analog components like LDOs, VCOs and HPMs were modeled using Verilog-AMS and run on the digital engine. This provides the framework to run highly accurate DVFS operations for dynamic power management.

With this approach, complex interactions between the analog and digital domains can be precisely executed and measured, errors detected, and metrics collected on the full SoC. Error detection and coverage span across digital/analog boundaries to include the full chip. The concepts and techniques of metric-driven verification methodologies are applied with the help of an executable verification plan to achieve functional closure.

Figure 2 - Precise controlled adaptive voltage and clock scaling

This is the last of a series of blogs on this topic...

For more details, the author can be reached at nkhan@cadence.com.




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