Last week a large number of customers and potential customers attended the “System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop” sessions in Irvine, San Diego, and San Jose. They must have been monitoring sub-space communication channels or read this blog post to find out about it.
Anyhow, I think the groups really “got it”. They could see the whole story. And how Cadence was delivering something unique…
- InCyte to create an early plan for the design & the impact of selecting various power strategies…
- C-to-Silicon to generate RTL from C making power-conscious trade-offs of big/fast vs. small/low power.
- Getting a full picture of the power behavior of the circuit with software running on an emulation of the circuit in Palladium-DPA.
- And finally double-header of analyze and optimize with RTL-Compiler design exploration to synthesize a variety combinations of multi-supply voltage, but keep the size and performance on target.
Can I drive? Can I drive?
But most of all, the groups liked spending hands-on time with the software. They ran through design examples in InCyte Chip Estimator. Sure, they followed the labs, but inevitably, they liked to take it “off-road” and start trying to build their own design and see what it would look like. One guy was building his own single-chip iPhone based on the iPhone under the hood article in EEtimes.
One potential customer commented on their view of the impact of InCyte:
“I can see where having an early chip plan can make a huge difference in my overall project cost! If I put a bit of time into the planning of power architecture, I can reduce power and reduce the pin-count of power/ground pins and pop my chip into a smaller, cheaper, cooler package. And that could make the difference between being profitable or not for my entire project.”
“Logical. Highly logical, Captain.” as Mr. Spock would say.
I think you can still register here for Austin (4/28) Arden Hills (4/30), Chelmsford (5/5) and Ottawa (5/27).
++ Mike Carrell