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Verification IP: Five More Things I Learned By Browsing Cadence Online Support

Comments(0)Filed under: Verification IP, PureView USB 3.0 VIP., PHY DUT, NVMe PureView VIP Usage, Verification Flow USB, Instantiating VIP models with SystemVerilog, Integrating USB 3.0 PHY DUT, Denali Migration Guide, USB, NVMe

After talking about some tips for using trace files in debugging Verification IP simulations in my last blog post, here I am back again, as promised. This time I'll discuss and provide references for the Denali Migration Guide, NVMe PureView VIP Usage, Verification Flow for USB, Instantiating VIP Models with SystemVerilog, and finally Integrating USB 3.0 PHY DUT with PureView USB 3.0 VIP.

1. Many users have reported that they face issues in transitioning from the Denali Software Memory Models (MMAV) and PureSpec (bus VIP - now PureView) to the Denali versions of the same Verification IP within the Cadence Memory Model Portfolio and VIP Catalog.

To resolve those issues, Cadence VIP R&D and engineers (Josue Reyes, Ryan Badger and Amy Witherow) immediately provided a simple and effective migration guide, Denali VIP Migration Guide which is intended to help users migrate from Denali VIP software/licenses to the Cadence VIPCAT software release. It should be very handy in that migration.

2. The growth in usage of the PCI Express interface, and its different implementations offering different subsets of features, generated a need for a protocol standard that defines standard drivers and interoperability between implementations to shorten qualification cycles.

The NVM Express standard was designed to enable faster adoption and interoperability of the PCI Express interface. Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It defines a register-level interface that allows communication with non-volatile memory.

Mukul Dawar, Sr. Solution Engineer at Cadence, wrote the NVMe PureView VIP Usage Application Note. This document illustrates the steps that are needed to set up the NVMe (on top of PCIe PureView VIP) PureView model with the DUT, including how to set up memory areas (LBAs and PRP List). Examples (code snippets) are provided to explain how a user can create/send different admin and IO NVMe commands.

This document covers the integration and use of NVMe PureView VIP when performing verification of RC-Host and/or EP-Controller DUTs.

3. Nikhil Sharma, Sr. Solution Engineer at Cadence, provides help for all users of the PureSpec USB2.0, USB 3.0 and SSIC VIP from the Cadence VIPCAT 11.3 release in his latest Application Note titled Verification Flow for USB VIP. Here he helps define next level of integration for first time USB VIP users, and shows how to make sure that the right steps have been followed before VIP is ready to send USB transfers from test cases.

4. The Verification IP group at Cadence is also introducing a new form of instantiation to enhance the usability of VIP models in SystemVerilog -- a new kind of HDL instantiation interface that allows the user to connect to a VIP model using a SystemVerilog interface as a port. Kathy McKinley, VIP R&D, wrote the Application Note Instantiating VIP Models with SystemVerilog to explain this new functionality.

SystemVerilog users who want to connect to a VIP model using SystemVerilog port interfaces can take advantage of the new functionality rather than using a portmap to our model with their own SystemVerilog interface. Having the VIP nets bundled to share and pass to the user environment is a valuable enhancement. Users will also enjoy direct access using the SystemVerilog language.

This feature is available in a new Verilog/SystemVerilog integration library that is based on the IEEE 1800 VPI (Verilog Programming Interface). This means that instead of loading libdenver.so or mtipli.so files for simulation, the user will load the new library, libcdnsv.so. The VIP scripts provided with the release and irun provide options for choosing the new library.

The new functionality is for static module instantiation. UVM dynamic instantiation will be supported later. 

5. Setting up a verification environment for a USB 3.0 PHY design core can be one of the most challenging aspects of verifying a SuperSpeed Design. The PureView USB 3.0 VIP not only provides a simple way to set up the testbench for verifying a USB 3.0 PHY DUT, but also maintains a powerful capability to verify the PHY DUT "in and out."

Nikhil Sharma's new Application Note Integrating USB 3.0 PHY DUT with PureView USB 3.0 VIP highlights important facts that are required to set up the testbench for possible configurations of PureView USB 3.0 VIP to verify a USB 3.0 PHY design core. This AppNote is geared to users of the PureView USB 3.0 VIP from the Cadence VIPCAT 11.3 release, and it will help users in integrating USB 3.0 PHY DUT with USB 3.0 VIP in all possible configurations.

Please login with your Cadence credentials at http://support.cadence.com to access the troubleshooting documents, Application Notes, videos and Rapid Adoption Kits from Cadence Online Support -- the Cadence Self-Help and Learning Portal for its customers. 

In my next blog, I will be introducing you to VIP Rapid Adoption Kits (RAKs) and illustrate a self-paced and complete workshop on Integrating USB3.0 and PCIE2.0.


Happy Learning!

Sumeet Aggarwal

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