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Bluespec and Cadence: Connecting Virtual Prototypes to FPGA-Based Prototypes

Comments(0)Filed under: Industry Insights, DAC, TLM, virtual platforms, Accellera, Cadence, SCE-MI, System Development Suite, Virtual System Platform, Rapid Prototyping Platform, VSP, Design Automation Conference, RPP, virtual prototypes, video, transaction level modeling, DAC 2013, Bluespec, FPGA prototypes, George Harper, FPGA-based, transactors, Transactor Gateway

Virtual prototypes and FPGA-based prototypes are both increasingly essential development platforms, each with distinctive advantages and tradeoffs. What if we could take the best of both and create a more integrated environment? In a recent video, as well as a recorded Cadence Theater presentation at the Design Automation Conference, speakers from Bluespec and Cadence showed how such an environment can be developed.

Cadence partner Bluespec sells tools and IP that support the early use of emulation and FPGA-based prototyping. A product called Transactor Gateway helps automate the creation of "hybrid" environments that connect virtual prototyping tools (such as the Cadence Virtual System Platform (VSP)) with FPGA-based prototyping tools (such as the Cadence Rapid Prototyping Platform (RPP)).

The video clip below shows how Cadence and Bluespec used the Accellera Systems Initiative Standard Co-Emulation Modeling Interface (SCE-MI) to link a software simulation environment to the RPP. SCE-MI integrates software simulation with hardware-assisted verification, allowing the same models to be used in both. This is made possible by models at the boundaries called "transactors." EDA vendors widely support the current SCE-MI 2.1 standard.

SCE-MI Bridges the Gap

In the video, Todd Snyder, senior design engineer at Bluespec, notes that Cadence and Bluespec joined forces to help a customer integrate some of their IP using the RPP. He said that Bluespec provided the SCE-MI connection that allowed the customer to integrate their testbench code—whether written in C,  C++ or SystemC—into the RPP system, where it could talk directly to the device under test (DUT). The benefit of SCE-MI, Snyder said, is that you write your testbench code only once, and you can then run it in both simulation and hardware-assisted platforms.

Matthias Kupka, senior sales technical leader at Cadence, noted that the starting point of the joint effort was to develop the SCE-MI-based interface between RPP and the C++ or SystemC testbench on a host workstation. The next step was to bring Bluespec transactors into the RPP flow.

If video below fails to open, click here.

Best of Both Worlds

The Cadence Theater presentation was given by George Harper, vice president of marketing at Bluespec. Harper focused on Transactor Gateway, which also uses SCE-MI. "We are trying to take the best of two different worlds," he said. Virtual prototypes, he noted, run very fast and are terrific for software development and debugging. But sometimes you need to do software development or debugging with accurate RTL, and that's where the FPGA-based prototype comes in.

Transactor Gateway, he said, enables a "hybrid configuration for early software development." It sits between the host workstation and the FPGA prototyping system, and provides connectivity between the SystemC TLM world and the RTL environment. A portion of the Transactor Gateway runs inside the RPP, and another portion resides on the host. The tool supports various APIs and off-the-shelf transactors, and provides "raw access to SCE-MI that's extensible and configurable to your needs."

The end result: "You get very-high-speed software development, but with the accuracy you want. You get the speed and completeness of the virtual prototype model, but with the ability to integrate RTL directly into your virtual prototype."

An audio recording of Harper's presentation, with slides, is available here. The presentation was given Wednesday, June 5 at 11:30 a.m.

Richard Goering

 

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