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25 Years of Innovation at Cadence – 25 Key Milestones

Comments(1)Filed under: EDA, Palladium, ESL, CAD, Virtuoso, Si2, CPF, OpenAccess, IP, CAE, Metric-driven verification, VIP, UVM, emulation, Denali, Cadence, Tensilica, System Development Suite, IEEE 1801, FinFET, Verilog, system level design, Verisity, electrically aware design, Analog Artist, partial layout, Quickturn, SpectreRF, Tempus, EAD, frameworks, Tangent, 25th anniversary, Dracula, SDA Systems, 25 years, Cadence history, Power Forward, Gateway, ESDA, ECAD

Cadence is celebrating its 25th anniversary in 2013, and there's a long history of innovation to celebrate. We'll be highlighting some of that history over the next 12 months in blogs, videos, and other media. In this post, I'll point to some of the key contributions that Cadence brought into the world of electronics design, both through strategic acquisitions and internal development work.

As Brian Fuller recently wrote in his blog post, 25 Years of Innovation: Then, Now, and the Road Ahead, the world of electronics was very different in 1988 when Cadence was launched. PCs were around in 1988, but with a fraction of the power (and much more weight and cost) compared to today's PCs. Smartphones, tablets, and a consumer-centric Internet existed only in the imagination of a few visionaries.

The world of EDA was also very different in 1988. In fact, the term "EDA" had recently been coined to indicate the merger of computer-aided engineering (CAE), or front-end design, with CAD, or physical design. The big three CAE vendors in the 1980s were Mentor Graphics, Daisy Systems, and Valid Logic, and they all sold workstations along with their schematic capture and simulation software. They then added software for IC and PCB physical design, replacing 1970s CAD providers such as Calma, Applicon, and Computervision.

An Auspicious Beginning

Cadence was launched June 1, 1988, from the merger of two up-and-coming, software-only EDA companies -- ECAD Systems and SDA Systems. If we're going to talk about Cadence innovations, we should start with the innovations these two companies brought into the marketplace. ECAD pioneered the IC physical verification technology that became known as Dracula, one of the most successful and widely used EDA products of the 1980s and 1990s. SDA Systems worked with the University of California at Berkeley to create a "design framework" that enabled an integrated suite of tools for IC design.

So, call Dracula and the SDA framework innovations #1 and #2, and here's a list of 23 other innovation "milestones" from Cadence history. I wrote about many of these developments for EE Times. This is by no means a complete list, but I think it covers many of the highlights, and it shows a consistent trend of bringing new technology and new ideas to the marketplace.

  • 1989 - Cadence develops Analog Artist, an integrated custom IC design solution. It's the first product to use the SKILL language, which is today widely used for PCells, PDKs and tool customization.
  • 1989 - Following purchase of Tangent Systems, Cadence provides timing-driven ASIC placement and routing tools, and becomes the #1 provider in IC CAD.
  • 1990 - Following purchase of Gateway Design Automation, Cadence puts the Verilog language into the public domain, facilitating a transition from IC design with schematics to design with hardware description languages.
  • 1991 - Cadence releases Spectre, which provides up to 10X speedup over SPICE.
  • 1994 - Cadence popularizes some of the industry's first system-level design technology (then called electronic system design automation, or ESDA) following purchases of Comdisco Systems and Redwood Design Automation.
  • 1995 - Vampire, a hierarchical IC physical verification tool, succeeds Dracula.
  • 1998 - Cadence purchases Quickturn and later becomes the provider of Palladium emulation systems, making ongoing improvements to emulation hardware and software.
  • 2001 - Cadence donates its Genesis database to the Silicon Integration Initiative (Si2), setting the stage for today's widely used OpenAccess standard. (First production version of OpenAccess was provided in 2002, hence the "OpenAccess 10th anniversary" celebrations you may have read about last year).
  • 2001-2002 - Strategic acquisitions provide new IC design technology that Cadence brings to a broader market. These include CadMOS (noise analysis), Silicon Perspective (silicon virtual prototype), Plato (NanoRoute), and Simplex (signal and power integrity).
  • 2005 - Originated by Verisity and enhanced by Cadence, Specman verification environment pioneers metric-driven verification, verification planning, the verification language, and reusable verification IP.
  • 2006 - Power Forward Initiative, launched by Cadence, produces Common Power Format (CPF), the first power intent format available to the industry.
  • 2006 - Catena, a stealth-mode internal initiative, rolls out Chip Optimizer, which leads to the Virtuoso Space-Based Router - a pioneering custom/analog routing tool.
  • 2006 - Virtuoso adopts constraint-driven flow, uses OpenAccess (which provides a foundation for today's Cadence mixed-signal flow).
  • 2008 - Internal development effort results in C-to-Silicon Compiler high-level synthesis tool.
  • 2010 - Cadence expands IP and VIP portfolios in memories, high-speed interfaces, analog/mixed-signal, and dataplane processing units. Acquisitions of Denali, Tensilica, Cosmic Circuits, and Evatronix take place 2010-2013.
  • 2011 - In collaboration with other industry players, Cadence plays key role in development of the Universal Verification Methodology (UVM) standard.
  • 2011 - Cadence fields industry's first DDR4 and Wide I/O (for 3D-IC) IP solutions.
  • 2011 - Cadence System Development Suite offers a set of interconnected platforms for hardware/software co-development.
  • 2012 - Si2 donates CPF to IEEE 1801 (Unified Power Format, UPF) standards effort. Cadence plays key role in IEEE 1801-2013 standard, which offers "methodology convergence" between CPF and UPF.
  • 2013 - ARM and Cadence partner to implement a Cortex-A57 processor on a TSMC 16nm FinFET process. This follows several years of heavy investment by Cadence in developing tools for FinFET technology.
  • 2013 - Cadence introduces new static timing analysis technology with the Tempus product; parallelized computation offers huge speed and capacity advantages.
  • 2013 - A new Virtuoso technology called "partial layout" allows simulation of layout dependent effects before layouts are complete.
  • 2013 - Virtuoso Layout Suite for Electrically Aware Design brings a new methodology to custom/analog layout that uses in-design, real-time interconnect parasitic extraction.

Looking over this list, I have to wonder what the next 25 years will provide - both in terms of EDA innovation and electronics in general. We could hardly have imagined, looking forward from 1988, the world that we live in today. What 2038 will bring is probably beyond our imagination as well. But one thing that's clear is that continuing innovation in EDA will help create that new world - and Cadence will continue to be a major contributor.

Richard Goering

 

Comments(1)

By satish kumar gupta on August 1, 2013
Article is impressive enough to impulse me to explore some more tools of cadence and EDA companies. Thanks for such good article.

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