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Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

Comments(0)Filed under: Industry Insights, TSVs, DFT, ATPG, stacked die, DRAM, test, 3D IC, 3D-IC, Cadence, wide i/o, imec, boundary scan, IEEE 1500, MBIST, design for test, BIST, Petrakis, interposer, wide io, LBIST, known good die, post-bond test, 2/5D, interconnect tests, Keller, pre-bond test, built in self test, wafer test, memory on logic, 3D-IC DFT, Cadence and Imec

3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D-ICs, including 2.5D silicon interposer solutions and 3D die stacks with through-silicon vias (TSVs).

The new methodology is an enhancement of an automated 3D-IC test architecture developed by Cadence and imec in 2011 (described in an earlier blog post). This methodology was aimed at logic-on-logic configurations. What's different with the new solution is the focus on memory-on-logic, as well as the use of the Wide I/O DRAM standard supported by Cadence design IP. "The first [3D-IC] chips to enter the market will be memory on logic," said Bassilios Petrakis, product marketing director for Encounter Test at Cadence. "What's exciting is that we have the solution for what we think will be the first application of this technology."

3D-IC test is very challenging. Pre-bond test (or "wafer test") is required for the individual dies, and if they're in a stacked die configuration but not at the bottom, fine-pitch probing will be required for access. Post-bond testing assumes "known good dies," but this is not a 100% guarantee. There is no direct access to non-bottom dies, and in a memory-on-logic configuration, the DRAM dies can only be accessed through the logic die. That is true whether logic and memory dies are in a 3D vertical stack or placed side-by-side on a silicon interposer substrate (the so-called "2.5D" configuration).

Wrapping up Test

The 2011 Cadence/imec architecture was aimed at both pre-bond and post-bond testing. One focus was bringing test signals out to larger pads for pre-bond testing. For post-bond testing, the architecture defined ways to get test data to and from chips in a stack without consuming too many package test signals. The solution used the IEEE 1500 embedded core test standard to develop "wrappers" that allowed individual testing (or bypassing) of a die in a stack. These wrappers were extended to work in three dimensions.

The newly announced memory-on-logic work focuses on post-bond testing with an emphasis on interconnect. "The components in the stack are expected to have been tested prior to integration in the stack or interposer," said Brion Keller, senior architect at Cadence. "You need to verify that everything has been connected properly, and you can also do some limited retesting of the internals of the components, but the primary new thing you're testing is the interconnect."

The Wide I/O standard allows up to four DRAM dies, or "ranks," to be placed on top of a logic die or on an interposer substrate (left). Wide I/O also includes boundary scan features to facilitate interconnect testing. The Cadence/imec solution uses this capability by driving test signals through the logic die, which is where the DRAM controller is located. "It's a very simple boundary scan, no control registers, no state machines," Keller said.

The Cadence Wide I/O controller also has a memory built-in self test (BIST) solution that can pump data into the DRAMs and read it back. It's not a manufacturing test BIST solution, but it can run a functional test on the memories, providing another way to verify if the DRAMs are working properly.

"We insert test logic and control logic inside the logic die to apply patterns, and there are several scenarios," Petrakis said. "In one scenario the logic die is the master and is driving data through the logic and capturing it in the memory die. In another scenario, you load some data into the memory through the scan chain and capture that through the logic die."

Keller noted that the new solution generates two types of interconnect tests. One is a connectivity check between drivers and receivers on every net. Another is a shorted net test. While these two tests will catch opens and shorts, they won't find delay faults that affect system performance across the interconnect. The MBIST capability will catch delay faults, however, because it will run data transfers at system speeds. Thus, the combination of interconnect tests and MBIST provide a complete post-bond test solution.

Proof in Silicon

Any new design or test methodology is only as good as the silicon it produces. Cadence and imec verified the 3D-IC memory-on-logic test solution with an industrial test chip. This 2.5D test chip includes a silicon interposer base, a 94mm2 logic SoC in 40nm technology, and a single Wide I/O DRAM rank. The same DFT methodology will work for 3D stacked die.

The silicon area of the additional DFT wrapper was negligible (<0.03%), test pattern generation was efficient, and tests provided 100% coverage of the targeted faults. The DFT logic in the logic die was inserted with the Cadence Encounter RTL Compiler, and the interconnect test patterns were generated with Encounter Test ATPG. Further information is available in the imec press release.

This 3D-IC test announcement will not get the kind of notice that the next great consumer mobile device will get. But it just might make it possible.

Richard Goering

Source: Imec press release, Jan. 22, 2013

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