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Webinar Report: Speeding RTL and Gate-Level Simulation

Comments(0)Filed under: Industry Insights, RTL, SoC, Functional Verification, Incisive, Simulation, Debug, webinar, assertions, Cadence, Samsung, debugging, elaboration, Adam Sherer, simulation performance, gate-level, compilation, speeding simulation

Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the Cadence Incisive Enterprise Simulator, incremental elaboration, new gate-level methodologies, and performance audits.

The webinar ran Dec. 4, 2012 and was titled "Better Verification Performance - The Ideal Holiday Gift." It followed an earlier 2012 webinar (also archived) titled "Racing for the Chequered Flag: Tuning Incisive for Speed." While the earlier webinar focused on identifying bottlenecks in simulation scripts and the runtime environment, the most recent webinar, reviewed in this blog post, described more substantial changes you can make to improve performance throughout the compilation/elaboration, execution, and debug cycle.

Adam Sherer, Cadence product marketing director, began the webinar by noting that performance bottlenecks and requirements differ in each verification stage. For an IP team, for example, elaboration/simulation is fast, and analysis and debug is typically the bottleneck. For an SoC team, bug analysis is complex, but simulation is more of a bottleneck. Everyone, however, wants fast turnaround times and an optimal work environment.

Sherer presented a detailed chart that showed how Cadence has optimized and improved various elaboration and run-time features from Incisive releases 9.2 to 10.2, 10.2 to 11.2, and 11.1 to 12.1 (the latest release is 12.2). This chart represents a three-year period. Cumulative performance gains during this period range from 1.2X for VHDL RTL to 19X for coverage writing, a more recent simulation feature.

In the spirit of what's possible, Sherer discussed a collaboration with Samsung that resulted in a considerable simulation performance boost (you can read the full story here).  Working with Cadence, Samsung was able to reduce RTL regression time by 80% -- from 5 days to 1 day - and gate-level regression time by 60%. Samsung achieved a 1.5X speedup for gate-level simulation with timing and 2.2X for zero-delay gate-level simulation. Long-running RTL simulation time was reduced from 100 hours to 4 hours, and simulation environment builds decreased from 315 to 20.

Working Out of the Box

Gagandeep Singh, staff product engineer, gave an overview of a number of "out of the box" performance improvements available today in Incisive. These enhancements boost gate-level, SystemVerilog, and assertion performance. A few examples of specific enhancements include:

  • Sharing infrastructure and optimizations for gates and complex continuous assignments (gate level)
  • Optimized equivalent gates with complex input conditions (gate level)
  • Optimized dynamic wait list on unpacked arrays (SystemVerilog)
  • Elaboration optimizations for large number of classes (SystemVerilog elaboration)
  • Multi-cycle optimizations (assertions)

He then talked about incremental elaboration, which makes it possible to bring IP into an SoC flow without having to re-compile and re-elaborate every time a simulation is run. Incremental elaboration makes it possible to create multiple instances called "snapshots." A pre-built snapshot that contains relatively stable parts of the model is a "primary" snapshot. The final snapshot, which links together primary snapshots, is an "incremental" snapshot. If there is a change in a snapshot, it can be compiled independently.

Singh then talked about gate-level methodology improvements, first presenting a Cadence customer survey that showed substantial use of gate-level simulation. Reasons for running gate-level simulation include reset verification, X (unknown) optimism in RTL, timing verification on multi-cycle paths, and "basic heart-beat test." One methodology suggestion is to run more zero-delay gate-level simulation, which offers a 3-4X performance improvement over full timing simulations. A "timing file" can turn timing on or off for particular instances of a design.

Finally, Singh talked about performance audits. "We partner with our customers to get a better overall performance in simulation in their real work environment. We have a well structured process that's driven by a Cadence expert team. We have seen gains ranging from 2-3X within one or two weeks at multiple customer sites." He also noted that application notes on improving simulation performance are available through Cadence Customer Online Support.

"The performance challenge we have for SoC verification is a big one," Sherer concluded. "At Cadence our responsibility is to get you a good simulator, good analysis tools, and new methodologies to improve performance. There's going to be a lot of information sharing."

To view the webinar, click here (Cadence Community log-in required - quick sign-up if you don't have one). To read a detailed whitepaper on improving simulation performance, click here.

Richard Goering

 

 

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