Home > Community > Blogs > Industry Insights > interconnect workbench eases analysis and verification for arm based socs
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

Comments(0)Filed under: Industry Insights, ARM, IP-XACT, verification, IP, Incisive, VIP, UVM, AMBA, EDA360, SystemVerilog, ARM Techcon, e language, VIP Catalog, Steve Brown, cache coherency, testbench, interconnect, performance analysis, Interconnect Workbench, traffic generator, SoC: verification IP, systems architect

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness. A new software tool, described in a recent ARM guest blog, promises to ease both these tasks with a new level of automation.

The tool is the Cadence Interconnect Workbench, and it has two use models. First, it provides a graphical performance analysis capability that helps system architects run what-if experiments quickly with different interconnect configurations. Secondly, it automatically generates a verification environment that includes a UVM e or SystemVerilog testbench, configures VIP that applies stimulus and response to the interconnect, and builds a verification plan that tracks coverage metrics.

"The problem that we're solving is that large SoCs are becoming too complex to do decent architectural planning, and the interconnect must be verified as IP itself," said Steve Brown, product marketing director at Cadence. "People do ad-hoc planning with spreadsheets because there is no more accurate alternative." The new tool provides an accurate alternative, and it works with the ARM AMBA protocol and all of its sub-protocols, like AXI, AHB and ACE.

Generating Testbenches

The diagram below shows how Interconnect Workbench works. It takes in automatically generated interconnect RTL and an IP-XACT metadata description from the ARM AMBA Designer. It also takes in traffic profiles and AMBA VIP. (There is no need to wait for RTL for the IP blocks or memories - the tool uses traffic generators instead). The Interconnect Workbench builds either a performance-oriented testbench or a verification oriented testbench. It can build a complete UVM testbench in minutes, enabling quick "what if" experiments.

Overview of the Interconnect Workbench

When the goal is performance analysis, the Interconnect Workbench adds AMBA traffic generators and a performance monitor to the testbench. "We create a simulation-based performance test environment that uses the interconnect RTL as a cycle-accurate way to represent what the performance of the SoC will be," Brown said. "Instead of RTL for the peripheral IP, you connect a traffic generator, or proxy, to master and slave ports. The tool tells you what you're driving into the SoC and how the interconnect reacts to activity from the SoC."

As a result, architects can create experiments that evaluate traffic profiles in different scenarios and consider tradeoffs that impact throughput, latency, and bandwidth. "Architects can set up and modify experiments much more easily than they could before," Brown said. "They're still going to make decisions based on their intuition, but they'll have an easy way to validate that their decisions have some credibility."

Interconnect Workbench can also build a testbench that's automatically configured for functional verification closure. Here, the tool configures the interface VIP needed to apply stimulus and response to the interconnect. It automatically generates a template verification plan that has the interconnect topology built in, setting the stage for metric-driven verification. Finally, it generates the infrastructure needed to run simulations on the Cadence Incisive simulator.

At present, Interconnect Workbench requires the use of Cadence VIP, and it makes use of the Cache Coherent Interconnect Monitor that is part of the VIP Catalog. While the Interconnect Monitor does checking, the Interconnect Workbench adds stimulus, a test suite, and a verification plan that can collect coverage metrics.

If you've read the EDA360 vision paper released in 2010, you may recall that it discusses the challenges faced by IP integrators and suggests that new tools and methodologies are needed to serve them. Interconnect Workbench is one such tool.

The Interconnect Workbench will be further discussed at the ARM TechCon conference 2:10 p.m. Oct. 30, 2012, in presentation ATC-110 - "Cache Coherent Interconnect Complexity, Verification, and Performance Analysis" by Nick Heaton (Cadence) and Paul Martin (ARM). To read an ARM guest blog about Interconnect Workbench, and view a short video demo, click here.

Richard Goering

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.