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IP Talks! Video – ARM’s John Heinlein Cites SoC Success Requirements

Comments(0)Filed under: Industry Insights, ARM, DAC, chip estimate, SoC, IP, ChipEstimate, TSMC, Cortex-A15, 20nm, Cadence, John Heinlein, IP Talks!, ChipEstimate.com, Cortex-A7, videos, DAC 2012, IP Talks, big.LITTLE, processor optimization packages

John Heinlein, vice president of marketing for the Physical IP division at ARM, believes that an advanced system-on-chip (SoC) design shouldn't be a "leap of faith." In a keynote speech at the IP Talks! sessions at the ChipEstimate.com booth at the Design Automation Conference (DAC 2012) - and now available by video - Heinlein talked about what it takes to deliver timely, predictable results with complex SoCs.

Heinlein's speech, titled "Realizing the Next Wave of Smart Devices," was one of around 40 IP Talks! presentations over a three-day period. These interactive 10-20 minute presentations by IP providers covered just about every important aspect of IP and SoC design. Videos of the presentations are now available at ChipEstimate.com.

John Heinlein gives keynote speech at IP Talks! at DAC 2012

Heinlein began his talk by looking at trends in mobile devices. But he didn't just talk about smartphones and tablets. Noting that every 600 smartphones require a server, he also noted that ARM and its partners are working to enable cloud computing by delivering server platforms that are customized and energy efficient.  "Server farms are all about how much processing you can deliver for a given heat budget," he said. "We expect to see a 20X increase in Internet traffic over the next four years."

So what's required to achieve reliability in silicon for smart devices? Heinlein identified three criteria:

  • A rich, full, IP solution that is proven and reliable
  • EDA support at advanced nodes
  • Early collaboration between EDA, IP, foundries, and semiconductor companies

Much of the talk focused in IP, and Heinlein immediately made it clear that ARM's offerings go far beyond processor IP. He talked about the software infrastructure that ARM provides;  physical IP that specifically targets ARM cores; cache coherent interconnect IP; memory controllers and PHYs; and the processor optimization packs (POPs) that ARM has developed to help design teams get products to market quickly.

Heinlein also talked about "right size computing" and discussed ARM's big.LITTLE architecture, which pairs a high-performance Cortex-A15 processor with a small, simple, energy-efficient Cortex-A7 processor. The Cortex-A15 handles peak performance while the Cortex-A7 runs less demanding software. "It's like having a Prius with a Ferrari engine under the hood," Heinlein commented.

Heinlein noted the 2011 collaboration between ARM, TSMC and Cadence that produced a 20nm test chip using the Cortex-A15. "The point here was to grease the skids, to make sure we've checked out all the issues so by the time you get to your design with this advanced technology, everything has been proven and tested," he said. "Using the advanced process technology from TSMC, the advanced physical IP and cores from ARM, and the tool chain methodology from Cadence, it ended up with a very successful result."

You can watch the video by clicking here (may require log-in or quick registration) or by clicking on the icon below.

 

Videos are also available for IP Talks! presenters from Arasan, Cadence, CAST, eSilicon, GLOBALFOUNDRIES, Open-Silicon, Samsung, Silicon-IP, Synopsys, True Circuits, TSMC, and Xilinx. Some of these companies had multiple presenters, as did ARM. See the ChipEstimate.com video site for a complete listing.

Richard Goering

 

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