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Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow

Comments(0)Filed under: Digital Implementation, encounter, ECO, rtl compiler, low power, mixed signal, Encounter digital Implementation system, mixed-signal, 3DIC, 3D, 3D-IC, silicon realization, Digital end-to-end flow, Encounter Test, gigahertz, giga-gate, Conformal

It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more?

Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the semiconductor industry?"

If the latter is your new year's resolution, then I am excited to tell you about a flow that was unveiled today (Jan. 31, 2011) and can help you achieve it. Just hours ago, we unveiled the Cadence Digital End-to-End Flow, an integrated RTL-to-GDSII flow that we believe is the next step forward in digital design, implementation and verification. This includes the award-winning Encounter Digital Implementation System (including implementation and in-design signoff technologies), Encounter RTL Compiler, Encounter Conformal technologies (including Logic Equivalence Checking, ECO Designer and Conformal-LP), as well as Encounter Test.

Corporate marketing phrases aside, the Cadence digital end-to-end solution is actually the result of countless hours of listening to our customers and partners, prioritizing what needs to be done to enable the next generation of digital designs, and then hunkering down to implement them in the software.

What our Customers Have Asked For

We've learned a lot from our customers and the semiconductor industry in general, and I'd like to share a little about what we've learned. We knew performance requirements and the sheer size of today's designs would outgrow EDA capabilities if we didn't do something about it. The walls between synthesis and physical implementation are coming down quickly, as physical effects play a more important role up front. Also, the amount of manual work required for large-scale ECOs has become unmanageable.

Besides those core requirements stated above, there are design categories that were previously considered non-mainstream designs, but are considered mainstream today -- namely, mixed signal and low power designs. As custom designs grow in size and complexity, the automation provided in digital solutions is a natural progression in terms of productivity -- but only if the digital tools are made accessible enough to custom designers, in terms of tool familiarity, and of course the ease of maintaining design intent and database coherence between the two domains.

As power consumption targets become a hard requirement instead of the "see how much we can save" approach, designers are paying more attention to having convergence to a set power target throughout the design flow. This means designs have to meet all requirements -- power, performance and area, and often in that order, especially for mobile devices. In other words, there's no backing out of power requirements just to meet timing.

Finally, leading-edge customers of ours want more integration of advanced technology. As 28nm/32nm processes gain popularity and process design rules become more complicated, it is important for EDA companies to collaborate with foundries to streamline the handling of the newer design rules. Vertical chip packaging schemes are being extended to the SoC level, introducing a new category -- the 3D stacked die design environment. This will bring about significant benefits, including the reduction of interconnect bottlenecks and the ability to have heterogeneous processes coexisting in the same package. But these benefits also introduce new challenges to the design methodology.

The Cadence Digital End-to-end Flow

So, how does the Cadence digital end-to-end flow address the challenges outlined above?

We have updated the core design closure engines. Logic synthesis now has improved physical awareness, resulting in a more convergent RTL-to-GDSII flow. Physical implementation optimization engines have been vastly improved with an in-design advanced analysis engine that provides ultra fast, concurrent signal integrity and timing analysis that is capable of reducing SI closure runtime by half, and reduce iterations by providing more convergence. We also now have a standardized, single-option high effort flow that can be put through the toughest, most timing-critical designs, as opposed to requiring the designer to come up with a custom script. This design closure methodology fully supports 28nm/32nm design rules. In fact, we have streamlined 28nm/32nm rule support such that routing speed for 28nm/32nm designs in this release has been sped up by 2X compared to the previous 9.1 release.

To address designs in the 100 million instances range, we have developed new data abstraction technology that provides a new way for entire blocks of logic to be modeled simply and accurately, resulting in runtime improvements of 20X or more. This enables designers to tackle ultra-large designs with reasonable runtime. Also, to address the ever-increasing number of hard macros on a design, we have revamped our automatic macro placement engine to be more intelligent than before, and to produce results that resemble hand-placed floorplanning.

ECO-weary customers (i.e. everyone in semiconductor design) can expect significant improvement in the way large-design ECOs are done. With the Cadence ECO Designer,  part of the digital end-to-end flow, we now have a much more automated way of implementing RTL ECOs all the way from ECO synthesis to physical implementation. The bottom line is: more automation in generating the ECO netlist, and more automation in implementing that netlist with your ECO cells.

We have also enhanced our constraints-driven mixed signal flow, allowing intent to be effectively conveyed between digital and custom design. Among the enhancements is the ability for accurate full mixed-signal static timing analysis and timing-driven physical implementation to eliminate iterations between analog and digital design teams. Low power designers will benefit from more automation and ease-of-use in our correct-by-construction approach. A notable improvement is the power intent architect, which is a much-requested feature that allows power intent to be created and validated by the tool, using an intuitive user interface. A second highlight is an enhancement to physical synthesis to enable smarter clock gating through Clock Topology Planning (CTP); leveraging physical information early in the flow during synthesis to create smarter clocks, leading to lower power chips.

Last but not least is something that I am very excited about, not only because it's a significant leap forward in terms of chip design and packaging, but the potential it has to bring about some major breakthroughs in chip design: 3D-IC design. The Cadence digital end-to-end flow includes the first production release of a fully integrated 3D-IC design environment. In short, we now have a full-featured consistent design, implementation and verification environment across digital, full-custom, and packaging environments, driven by unified 3DIC design intent, that allows designers to fully realize their 3D-IC design and benefit from the ability to reduce interconnect bottlenecks and realize heterogeneous processes on a single package.

What Does This Mean to You?

Last October Cadence announced our new approach that delivers a deterministic path to Silicon Realization by creating a design flow based on the three requirements of unified design intent, design abstraction and design convergence. In other words, by providing a flow in which design intent is pervasive (instead of having different parts of the flow interpret design intent differently), uses the appropriate levels of abstraction (such as hierarchical abstraction, or other modeling technologies such as the new advanced analysis engine for signal integrity and timing) to deliver better speed and capacity, and last but not least, ensuring a highly convergent flow, we aim to provide you with the solution that gives you fastest path to successful silicon.

The Cadence digital end-to-end flow is part of our Silicon Realization goal. But don't just take our word for it -- as you hear more about it in the coming months, I invite you to give it a try, and if you already have, feel free to comment below on your experiences so far.

What's Next?

You can find out more about the Cadence digital end-to-end flow from the article located here. Or, check us out this week at DesignCon 2011. Hope to see you there!

Wei Lii Tan

 

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