Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> specman/Aspect Oriented Programming
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
specman,Aspect Oriented Programming
ABV
advanced verification
AF
AMIQ
AMS
AOP
assertion synthesis
Avi Behar
Cadence Connections
Cadence VIP portfolio
CDNLive
CDV
CFS Vision
ClubT
CMS
constraints
coverage driven verification (CDV)
Coverage-Driven Verification
DAC
debug
DVcon
e
e language
EDA
EDA360
Enterprise Manager
Enterprise Planner
eRM
ESL
formal
Formal Analysis
FOSS
Funcional Verification
Functional Verificatioa
Functional Verification
funtional verification
HW/SW
IEEE 1647
IES
IES-XL
IEV
Incisive
Incisive Enterprise Simulator (IES)
IntelliGen
ISX
ISX (Incisive Software Extensions)
JFreeChart
job postings
Jobs
Kaberi
Low Power
MDV
methodology
metric driven verification (MDV)
Mixed Signal Verification
Multi-domain verification: HW/SW co-verification
Object Oriented Programming
OOP
Open Verification Methodology
OVM
OVM e
OVM ML
OVM-e
OVMWorld
sequences
Shneydor
signal integrity
Silicon Realization
simulation
SimVision
SoC
specman crashes
specman elite
specman job postings
Specman/e
stack trace
SVA
System Verification
SystemC
SystemVerilog
team specman
tech tips
testbench
Testbench simulation
TLM
Trailblazer
UVC
uvm
UVM e
UVM-e
verification
Verification methodology
verification strategy
VHDL
VIP
vPlan
vr_ad
when sub-typing
workshops
Zocalo
New OVM-e Testflow Features Introduce Increased Automation
Hi All, With the release of the OVM- e library, there are now many new features available for users to take full advantage of. I would like to discuss one new feature that, when introduced into a users environment, allows for much greater automation and control over a given simulation run. The e language...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Feb 25 2009
Grey-Boxed Data-Path Approach Using 'when sub-typing'
[Please join Team Specman in welcoming the first guest blogger from our user base: Ms. Kaberi Banerjee, a senior design & verification engineer based in Silicon Valley California] Fellow Specmaniacs (or should I say "specmites" – in alignment with the subject of bugs!), I recently...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Feb 18 2009
Tech Tip - Double Wall Clock Performance with One Easy Step
[Please welcome guest blogger Silas McDermott, an Application Engineer in our Field Organization] There is one very easy step that Specman users can take to roughly double the wall clock, run time performance of their testbench. In a word, "compile"! That's right: by simply compiling their...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Feb 6 2009
"...Yes, Virginia there is a Specman"
I usually try to visit many of our customers in Europe (and other parts of the world) at least a couple of times a year. On my last trip in October, while I was in Stockholm, I ended up having beers at a pub with one of our local AEs and a Specman customer. This customer had been telling me about all...
Posted to
Functional Verification
(Weblog)
by
mstellfox
on Mon, Feb 2 2009
"ClubT" Newsletter Issue #3 Just Posted
Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter is now posted here , and once again there is exciting news around e , Specman, and Verification. Articles include: * Have you heard of OVM e ? * Incisive 8.2 Technology Update * Verification IP Portfolio E-x-p-a...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 27 2009
The New Generation Testcase Utility
Specman's new Generation Engine, "IntelliGen", adopts an entirely new generation scheme compared to the previous engine, "Pgen". It groups fields which are related via constraints into a Connected Field Set (CFS) and automatically determines the order in which all CFSs must be...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Jan 8 2009
The Eternal Debate: "Like" vs. "When" Inheritance
First: Happy New Year, Specmaniacs! Much like the rivarly between the New York Yankees and the Boston Red Sox (or if you prefer, ManU vs. Chelsea, or the Tokyo Giants vs. Hanshin Tigers, or [insert a cricket example here]), Specmaniacs have been divided into two competing camps, with one group favoring...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Jan 5 2009
Constraint Layering - Fine Tuning Your Environment - Part 2
In my last post , I talked briefly about constraint layering in which I gave an extremely simple example of how users can layer constraints on an existing base environment to change how that base environment behaves, all without touching the base environment. Obviously, we all know that our verification...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Dec 12 2008
Constraint layering - Fine Tuning Your Environment - Part 1
In today's environment of ever growing complexity and ever shrinking schedules, simplifying verification code reuse and maintenance is a clear necessity. To that end, this entry is dedicated to the concept of "constraint layering" in e . This concept is incredibly useful in addressing many...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Dec 10 2008
Page 4 of 4 (39 items)
< Previous
1
2
3
4