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cadence,Spectre

  • Monte carlo analysis

    sir i am ,, using IC 5.10.40 in cadence , ,, I want to make monte carlo analysis for my circuit , but my seniors here are telling that monte carlo is not working here in the version ,, how can i check that ?.. i am just beginer , please reply ,,
    Posted to RF Design (Forum) by rakesh reddy on Thu, Mar 20 2014
  • fully differential opamp .. how to calculate cmrr ??

    I made this schematic and I simulated this I am getting gain ~40dB and UGB 20Mhz, I want to do stability analysis for this fully differential ckt , And I want to find out --- CMRR --- PSRR ---Loop gain (from stability analysis ) How I should use cmdprobe to do stb analysis , please help me ,, adrew sir...
    Posted to RF Design (Forum) by rakesh reddy on Mon, Feb 17 2014
  • how to measure power consumption of a circuit in cadence spectre

    Hi, I would like to know how can I estimate the power consumption of a circuit say an inverter circuit in cadence environment. I searched through the internet, but couldn't find any suitable doc that is helpful in this regard. I am looking for the steps required for power estimation. Thanks &...
    Posted to Custom IC Design (Forum) by indra0804 on Sun, Sep 8 2013
  • (IC6.1.5.500.12) ADE L messing up sim results(result access). Anyone familiar with that?

    Dear All, I've done extensive searching on forum for this, in vain. However, I am sure that someone else came across this, and maybe my search keywords weren't appropriate. If you know of thread relating to this, please point me to it. From time to time I get the those symptoms (they might all...
    Posted to RF Design (Forum) by ChrisXB on Fri, Jul 19 2013
  • Noise sources in PSS analysis

    Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...
    Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
  • Re: Problem in Cadence Virtuoso AC analysis

    Hi Andrew, I had a little doubt on what parameters are explicitly needed for ac analysis. This is because I am using verilog -A based models and hence want to be sure if I am doing the right thing. As far as I know, AC analysis first computes the DC operating point: so I must define current at each operating...
    Posted to Custom IC Design (Forum) by OneNewBoy on Mon, Mar 25 2013
  • Re: Different op amp gains using different spectre analysis

    Thanks for reply, However I am facing a very strange problem in my simulation, please help me with this: I am running a parametric simulation to experiment & get the optimal bias current of Op-Amp . For this I gave a list of "I_bias" as "5u 7u " in the parametric analysis window...
    Posted to RF Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • Different op amp gains using different spectre analysis

    Hi all, I am new to analog design. I have created an op-amp schematic and tried to get open loop gain by 2 ways: (Simulation uses cadence virtuoso) 1) Transient analysis: applied a ramp pulse of 0->VDD to +ve input [with a dc value of VDD/2] and kept -ve input to Vdd/2, then plotted Vout vs V+ and...
    Posted to RF Design (Forum) by OneNewBoy on Wed, Mar 20 2013
  • Mixed Signal Technology Summit Proceedings Now Available

    In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
    Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
  • How Cadence Helps Universities Build EDA Infrastructures

    Many EDA companies, including Cadence, have university programs that make it easier for academia to acquire tools. But what about the software/hardware infrastructure that supports those tools? In this era of budget shortfalls, university compute infrastructures are under severe stress. Recently the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 7 2012
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