Home > Community > Tags > advanced node
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

advanced node

  • DesignCon 2010 Call for Papers

    Hello, As a member of the technical committee and as the chair member for the Analog and Mixed-Signal Design and Verification track, I would like to invite you to submit an abstract to this conference. We solicit papers for two types of sessions: technical papers and tutorials. Technical papers, which...
    Posted to Custom IC Design (Weblog) by helenet on Mon, Jul 20 2009
  • Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

    Some background info: Taking a quick look at Power dissipation in CMOS: Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture...
    Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 15 2009
  • Guest Blog: The RF Challenge In Portable Designs

    The need for RF integration in consumer electronics presents some tough challenges, says veteran electronics industry editor John Donovan. He notes several emerging approaches that might help ease the challenge. In simpler times most designs were digital. Add a few converters to handle I/O and you could...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 13 2009
  • Q&A Interview: Chi-Ping Hsu Describes 5 Cadence Initiatives

    Chi-Ping Hsu is senior vice president of research and development for the Cadence Implementation Products Group. He is responsible for analog design and verification, digital implementation and signoff, mixed-signal design and implementation, physical verification, DFM, and PCB and package design. In...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 25 2009
  • Cadence: Committed to DFM

    On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions...
    Posted to Digital Implementation (Weblog) by mchacko on Fri, Jun 19 2009
  • Analog Is Back – But Not Like You Think

    After taking a back seat to digital design for many years, analog is re-emerging as a key differentiator and competitive edge for IC vendors. But analog design today is very different from that of 20 years ago, and realizing that is critical for success. In a recent EE Times column , Planet Analog editor...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 18 2009
  • 45 nm Is Turning Point For Model-Based DFM

    A recent decision by TSMC to require model-based design for manufacturability (DFM) checks at 45/40 nm may push DFM into more widespread use. It’s coming too late for the several dozen DFM startups that were around a few years ago, but it could have a significant impact on IC design flows going...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 4 2009
  • Moore no More

    "The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months". This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com . This has, of course, surfaced because of the recent release of the Watchmen...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Fri, Apr 10 2009
  • Does Noise Analysis Accuracy Really Matter?

    There have been a lot of new faces springing up in the signoff analysis market over the past few years and the trend seems to be pointing toward products that deliver quick and reasonably good timing signoff with some signal integrity analysis tacked on as an afterthought. This prompted me to ask the...
    Posted to Digital Implementation (Weblog) by mikeNaustin on Tue, Mar 17 2009
  • Brad Griffin Speaks at DesignCon - Give Him a Listen!!

    If you were not lucky enough to be atDesignCon this week, and many of us were not! You might be interested in the streaming interviews posted on line. Click here for link. Scroll down the video soundbites in the right hand pane, list to what Brad says is the emerging trend and focus regarding today's...
    Posted to IC Packaging and SiP (Weblog) by SiPper on Thu, Feb 5 2009
Page 3 of 3 (30 items) < Previous 1 2 3