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advanced node

  • What’s Hot for Mixed-Signal At DAC?

    Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is...
    Posted to Mixed-Signal Design (Weblog) by QiWang on Thu, May 31 2012
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
  • Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

    As more and more custom/analog designs migrate to advanced process nodes (<65nm), design teams are being confronted with an ever-increasing need to better manage the impact of parasitics throughout the entire custom/analog design flow. In addition, more and more layout design teams are finding themselves...
    Posted to Custom IC Design (Weblog) by mrkelly on Thu, Mar 17 2011
  • 28 nm IC Design: The Devil Is In The Details

    Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die...
    Posted to Digital Implementation (Weblog) by Nora on Mon, Mar 14 2011
  • How DRC Plus Makes DFM Easy at 28nm

    Design for manufacturability (DFM) requirements have been a barrier for many design teams who are thinking about moving to lower process nodes. But can DFM actually get easier as process nodes shrink? That possibility is offered by DRC Plus (DRC+), a new technology developed by GLOBALFOUNDRIES in collaboration...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 25 2010
  • EDA360 And The "Paperback Computer"

    Have you ever heard an assertion that's so intriguing and farsighted that it sticks in your mind over a period of years; even decades? Imagine that the given thought is so resonant, that whenever a related innovation appears the idea is instantly recalled as if you were just talking about it. For...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, Jun 3 2010
  • User Interview: What to Expect At 32 nm and Below

    Norma Rodriguez, senior member of technical staff at AMD , has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted layout patterns as well as DFM tools. At the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 26 2009
  • Advanced Node Panel: Making The Case For Restricted Design Rules

    You would think that designers would not welcome restrictions on what they do, but panelists at the recent Design Automation Conference saw restricted design rules (RDRs) as a helpful and necessary step towards 32 nm/28 nm IC design. Panelists from AMD , TSMC , Texas Instruments , and Cadence spoke Monday...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 6 2009
  • Q&A Interview: Charlie Giorgetti Outlines Cadence Product Solutions

    Charlie Giorgetti is corporate vice president of solutions and product marketing at Cadence. In this interview, he discusses Cadence’s product strategy, and outlines five “solutions” that are the current focus of Cadence’s marketing efforts. These solutions will be highlighted...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 23 2009
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction. RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings...
    Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 22 2009
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