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Virtuoso

  • Things You Didn't Know About Virtuoso: Introduction

    A while ago, I somehow ended up on the mailing list of a rather odd catalog called "Things You Never Knew Existed..." I think I got on the list when I bought some stocking stuffers for my kids for Christmas-things like little plastic pencil sharpeners shaped like noses (yes, you have the right...
    Posted to Custom IC Design (Weblog) by stacyw on Tue, May 12 2009
  • Jurassic Park IV: The Return of ANALOG

    In the lab, no one can hear you scream! When I was getting my BSEE in the 1980s and studying analog and communications, my friends would say, “Why are you studying that old dinosaur, digital is where it’s at!”. Well, far from being consigned to the La Brea tar pit, analog is once again...
    Posted to Custom IC Design (Weblog) by NewYorkSteve on Tue, May 5 2009
  • EDA Industry Stays Ahead of Technology Curve

    The EDA Industry is the unsung hero behind for modern era electronic revolution since early 80s and gets the spotlight it deserves in the recent DAC newsletter . I would like to applaud the author Geoffrey James, for crediting the EDA industry in rising to the challenges associated with each and every...
    Posted to Digital Implementation (Weblog) by Nora on Tue, May 5 2009
  • An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso SpectreMDL

    The emergence of sub-micron technologies has enabled today’s designers to include various digital/analog/RF components in a single chip. The complexity of validating such designs has highlighted the necessity for a robust validation methodology and for an appropriate process for running efficient...
    Posted to Custom IC Design (Weblog) by helenet on Mon, May 4 2009
  • Porting EDA Applications To Multicore -- Part 2

    As noted in part one of this blog series, porting the Encounter Digital Implementation System (EDI) to multicore platforms was a challenging task. That’s no less true for Cadence’s efforts to parallelize the Virtuoso Spectre Circuit Simulator, although the challenges were somewhat different...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 30 2009
  • Getting a Feel for RF

    It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine titled “ Getting some basic RF experience ”. I was surprising pleased that somebody took the time to talk about how one might get the feel for RF. That is because what Bob talks about is more or less...
    Posted to Custom IC Design (Weblog) by TomC on Wed, Apr 29 2009
  • Porting EDA Applications To Multicore -- Part 1

    The EDA industry is gearing up for what may be its largest retooling ever – retrofitting or rewriting applications to run on next-generation multicore platforms. An inside look at how Cadence ported the Encounter Digital Implementation System (EDI) to parallel processing illustrates some of the...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 28 2009
  • OpenAccess, Its Just a Database…

    I suspect that in another year we’ll all stop talking about OpenAccess (OA) like it is something special and treat it the way it should be, that it is just another database. Having said that, I know I’m going to get plenty of email about my portrayal of OA from colleagues and others but that...
    Posted to Custom IC Design (Weblog) by TomC on Mon, Apr 20 2009
  • Virtuoso, the SATs, and the Dark Knight - Part II

    Well, are you still wondering what Virtuoso has to do with the SATs and The Dark Knight ? Well, thanks for indulging me, I hope the suspense wasn’t too much to bear! As I mentioned in part 1 , if you had taken the January 2009 SAT test, again, like my daughter did, you had this as one of your essay...
    Posted to Custom IC Design (Weblog) by mrkelly on Mon, Apr 6 2009
  • What’s all the Hoopla with PDKs?

    At a purely technical level, Process Design Kits are fairly innocuous. They are used to enable custom IC design flows. A Process Design Kit (PDK) includes device models, schematic symbols, netlisting procedures and parameterizable cell layout generators. Physical verification rule decks and a parasitic...
    Posted to Custom IC Design (Weblog) by Robin Sarma on Tue, Mar 31 2009
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