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  • Ten Things You (Probably) Didn’t Know About SKILL

    The Cadence SKILL language has received some press lately as part of an ongoing debate over process design kit (PDK) standards. This post isn't about that. Rather, it's about the story behind SKILL, a venerable language that's far more than just a format for describing PCells in custom IC...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 9 2010
  • Things You Didn't Know About Virtuoso: ADE XL Test Setup

    In my last post , I left you in suspense, with your mouse hovering over the words " Click to add test " in ADE XL. Clicking on this button will bring up the ADE XL Test Editor window (which should look suspiciously familiar) and a dialog asking you to point to the design you want to use. This...
    Posted to Custom IC Design (Weblog) by stacyw on Thu, Aug 5 2010
  • Virtuoso & Virtuoso xl Tutorial - 5.10 ??

    Dear all, Is any one have the tutorial for the virtuoso and virtuoso XL for 5.10* version? -p-
    Posted to Custom IC Design (Forum) by Peter123 on Wed, Aug 4 2010
  • how to set the tech purpose of 0 in an ASCII technolog file

    I know the purpose of 0 is reserved by the system. But if I would like to use the purpose of 0, what's the name should I use? I can find other reserved purposes, such as 250 for 'boundary", 237 for 'label'. It seems 0 for 'unknown', however, if I use the 'unknown'...
    Posted to Custom IC Design (Forum) by phenixgj on Mon, Aug 2 2010
  • Things You Didn't Know About Virtuoso: ADE XL

    I know, it's been a long time since my last post. You see, we've finally arrived at a topic near and dear to my heart -- ADE XL. The reason for my hesitation in approaching this topic is not that it's difficult, but rather that there's so much to talk about that it's hard to know...
    Posted to Custom IC Design (Weblog) by stacyw on Tue, Jul 27 2010
  • Multiple Model Files

    Hi, I am working on a circuit where I need multiple model files. The first one I am using is gpdk045, I tried modifying this file to use with transistors from the analog library. The problem I have is that my simulations are wrong whenever I use a transistor with the second model file it just produces...
    Posted to Custom IC Design (Forum) by Karo on Wed, Jul 21 2010
  • ARM And Cadence Get To The “Core” Of Mixed-Signal Design

    An increasing number of analog and mixed-signal designs in automotive, power management, wireless, medical, and industrial applications require digital control. But designing a state machine, and integrating the increasing amount of logic gates that implements it, has been challenging for analog designers...
    Posted to Custom IC Design (Weblog) by nizic on Tue, Jun 8 2010
  • How to create templates for vdd/vss nets in Virtuoso

    I am working on the layout of a full custom digital design in Virtuoso. I have now fixed my pitch for the vdd and vss nets. Can anyone tell me as to how i can create templates of some sort of a ruler/guide for these nets which can help me to see where my vdd vss nets/tracks would lie in the layout .It...
    Posted to Custom IC Design (Forum) by akbhide on Mon, May 17 2010
  • Re: VerilogA Problem in MMSIM-7.1

    Hi !! I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package - icfb 5.1.0 subversion: within Linux Fedora 11 and with TSMC 0.18um Design Kit...
    Posted to Custom IC Design (Forum) by Winglet on Fri, May 14 2010
  • the sample library in dfII

    hi,there i have added the rfLib library which located in $CDS/tools/dfII/samples/artist directory to the ic5141 usr6 through library manager. But when i add the balun_com instance to the schematic,and start the simulation in the ADE,it gives the error message as below: ERROR: Netlister: unable to descend...
    Posted to Custom IC Design (Forum) by minci on Sat, Apr 10 2010
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