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UVM

Free UVM Tutorial Boosts IC Functional Verification Skills

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 12 2012
Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study With the GoPro Hero2 Camera

Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses. Clearly both sides of the low power coin -- reducing generated heat and/or increasing efficiency to make the...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Sep 12 2012
UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation. Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 29 2012
Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Aug 27 2012
Q&A: Cadence VP Martin Lund Brings User Perspective to Semiconductor IP

Martin Lund joined Cadence in early 2012 as senior vice president of R&D for the SoC Realization Group. He hasn't worked for an EDA company in the past, but 12 years at Broadcom -- most recently as senior vice president and general manager of Broadcom's Network Switching Business -- gave...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 20 2012
Using Eplanner with UVM

I am trying to implement checkers in my UVM environment from my vPlan and to map them in Eplanner. However, in the Eplanner I can only see the checks that I implemented as assertions in interfaces but not the checkers I implemented as assertions in my UVM monitor. Could anyone explain me how should I...

Posted to Functional Verification (Forum) by rdalibor on Mon, Aug 13 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 8 2012

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UVM

Free UVM Tutorial Boosts IC Functional Verification Skills

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study With the GoPro Hero2 Camera

UVM Testflow Phases, Reset and Sequences

What Does it Take to Migrate from e to UVMe?

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Q&A: Cadence VP Martin Lund Brings User Perspective to Semiconductor IP

Using Eplanner with UVM

Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques