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SystemC

extract memory value in systemC

Hi all, I have 2 files. In file A.vhd, I model a memory using " type t_mem is array(conv_integer(BASE) to conv_integer(TOP-1)) of std_logic_vector(7 downto 0); variable mem : t_mem;". In file B.cpp, I use "rtl_mem_value.observe_foreign_signal(memory_path)" to extract memory value...

Posted to Functional Verification (Forum) by jxker on Tue, Dec 11 2012
IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

EDA standards are a crucial enabler of today's complex electronic design flows - and it takes a lot of hard work to create them. Few know this better than Stan Krolikoski, who got involved with VHDL standardization in the early 1980s and has taken a leadership role in standards development ever since...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 3 2012
Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM

One of the main benefits of moving the design entry point up in abstraction from RTL to SystemC/TLM is faster verification turnaround. Higher abstraction contains much fewer details, so simulation at that level runs faster and debug is much more productive. But in order to reduce overall verification...

Posted to System Design and Verification (Weblog) by Jack Erickson on Wed, Nov 28 2012
CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login. The paper entitled "High-level Synthesis on Video Processing ASIC" delivered by Yaniv Fais and Michael Zarubinsky of Freescale gives a great look...

Posted to System Design and Verification (Weblog) by Jack Erickson on Wed, Nov 14 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 8 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models

As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 17 2012
Free UVM Tutorial Boosts IC Functional Verification Skills

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 12 2012
Improving SimVision Fonts for Ubuntu

This article is a follow-up on an early 2012 article about using Incisive and Virtual System Platform on the Ubuntu operating system. Although the feedback has been positive, the one area that was not covered very well is the look of SimVision. When I wrote the original article I used Ubuntu 11.10, and...

Posted to System Design and Verification (Weblog) by jasona on Fri, Aug 17 2012
Whitepaper: Connecting Specman e Language to SystemC TLM Models

SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 13 2012

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SystemC

extract memory value in systemC

IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM

CDNLive paper: High-level Synthesis on Video Processing ASIC

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Webinar: New Interface Links Specman e Language to SystemC TLM Models

Free UVM Tutorial Boosts IC Functional Verification Skills

Improving SimVision Fonts for Ubuntu

Whitepaper: Connecting Specman e Language to SystemC TLM Models