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Simulation

  • Cadence Low-power Verification: Tear Down These Walls

    You've been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation? Got it. Mixed-signal? Yep. Every team with fingers in the power intent? For sure. Siicon...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, Nov 2 2010
  • What is the difference? Orcad 15.7 Vs Orcad 16.3

    Presently I am using Orcad 15.7 for Capture, CIS, Pspice, ...etc. I am looking to upgrade my version. I just want to know what is the major difference between Orcad 15.7 and 16.3 in all modules (i.e., Capture, Pspice, PCB..etc). And also I want to know the cost between Orcad 15.7 and 16.3....If there...
    Posted to PCB Design (Forum) by Alexander L on Sun, Oct 31 2010
  • PSpice Parameter Sweep with X Axis Variable

    Dear All, I have one circuit of Transistor where I want to check V/I Characterstics in different values of component. For that I am using Parameter Sweep, but when I am trying to change X Axis after parameter sweep its giving some error. In normal transient simulation I am able to change the X Axis but...
    Posted to PCB Design (Forum) by Parveen on Thu, Oct 21 2010
  • Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together

    This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 19 2010
  • CDNLive! Hot Topic – OVM-Based Verification for Analog and Mixed-Signal

    The Open Verification Methodology ( OVM ) has helped thousands of verification engineers build structured testbenches and run coverage in digital environments. Can the same advantages be leveraged to verify analog IP and mixed-signal SoCs? Yes, according to a paper planned for CDNLive! Silicon Valley...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 13 2010
  • Analog Coverage Metrics in Mixed-Signal Simulations

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 5 2010
  • CDF parameters and AMS netlister

    Hi, I'm trying to do a mixed signal simulation with AMS. In my analog design i use CDF parameters to set transistor sizes. However, the components from the tech-lib i use calculate area values from the length and width values. Because of the Ppar("var") value of the sizes, the area calulation...
    Posted to Custom IC Design (Forum) by ArjanVanHeusde on Wed, Sep 8 2010
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss the simulation of closed-loop voltage scaling for adaptive dynamic voltage and frequency scaling (DVFS). My previous blogs covered some of the...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 7 2010
  • 5 Tips to Help You Finish Your Low Power Design Tapeout On Time

    So you're about to start your first low power design. Or second, third, or fourth. As with many tapeouts, you know that with today's tight market windows, most likely the project will go off with a sprinting start (architectural planning), followed by an endurance test (designing and implementing...
    Posted to Low Power (Weblog) by Design4Life on Fri, Aug 27 2010
  • Dynamic Power Management – Closed Loop Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very...
    Posted to Low Power (Weblog) by Neyaz on Tue, Aug 24 2010
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