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Incisive

EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

EU-based Specmaniacs and "Trailblazers" rejoice: the annual ClubT series is back! As always, these free events feature direct contact with Cadence R&D and Methodology experts to share developments in advanced verification, updates to the "Trailblazer" program, and hear your emerging...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Sep 29 2009
Q&A Interview: Steve Carlson Discusses Cadence Mixed-Signal Strategy

Steve Carlson is vice president of marketing for low power and mixed-signal solutions at Cadence. In this interview, he discusses the increasing importance of mixed-signal SoCs, describes key challenges, and outlines Cadence strategy and solutions. Q: The term "mixed signal" has been around...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 28 2009
Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

Since your circuit always runs at low-power, your verification should too. To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively. In some cases that can result in tests that run faster with power analysis on than with...

Posted to Functional Verification (Weblog) by Team genIES on Wed, Sep 9 2009
Requirements for a Student Version of Specman/IES-XL?

Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by the back-to-school season: You may recall a question was posted to Mike Stellfox back in February about the availability of a limited, student version of Specman and IES-XL for the student's personal computer (vs....

Posted to Functional Verification (Weblog) by jvh3 on Tue, Sep 8 2009
Friday Fun: Adopting New Low-power Design Techniques

This week's episode has the Dante Semi team employing some new low power design techniques, and using Conformal Low Power to verify their implementation of them. You will also see how the verification team uses low power simulation with Incisive to functionally verify the behavior. It's all going...

Posted to Logic Design (Weblog) by Jack Erickson on Fri, Aug 21 2009
DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System Verification

One of the great things about DAC is the opportunity to meet new people and find out what kind of things they work on. This year I had the privilege of meeting Alicia Strang, a Verification Engineer, at Marvell Semiconductor . I first met Alicia when she was assigned as the moderator for the User Track...

Posted to System Design and Verification (Weblog) by jasona on Thu, Aug 20 2009
The Scoop on Tracking & Validating Formal Assumptions – You Don’t Need to Assume

" Tackling formal assumptions through verification planning " is a recent article by Chris Komar and Frank Armbruster that is available on EDN. This article has fun with the old adage about what happens when you assume but very quickly get serious and applies it to functional verification and...

Posted to Functional Verification (Weblog) by Sarah Lynne on Fri, Jul 17 2009
TLM-Driven Design and Verification Solution

At this week's CDNLive! Japan we made an important press release announcement about our new TLM-driven Design and Verification Solution, and delivered the first Techtorial covering the technology and methodology. The solution combines C-to-Silicon Compiler (CtoS) , Incisive Enterprise Simulator ...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, Jul 15 2009
Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator

When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many great features were available in the software which I did not know about as a designer. So much of my time was spent on design and verification, there was little time to explore all the capabilities of the software....

Posted to Functional Verification (Weblog) by hilker on Tue, Jun 30 2009
Create a Sine Wave Generator Using SystemVerilog

Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI. Obviously, to produce a sine wave, you need access to the sin function. This is where DPI is handy to add the math functions...

Posted to Functional Verification (Weblog) by tpylant on Tue, Jun 30 2009

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Incisive

EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

Q&A Interview: Steve Carlson Discusses Cadence Mixed-Signal Strategy

Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

Requirements for a Student Version of Specman/IES-XL?

Friday Fun: Adopting New Low-power Design Techniques

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System Verification

The Scoop on Tracking & Validating Formal Assumptions – You Don’t Need to Assume

TLM-Driven Design and Verification Solution

Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator

Create a Sine Wave Generator Using SystemVerilog