Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Encounter
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Encounter
"db access"
"SoC-Encounter"
14nm
20nm
28nm
3D
3D IC
3DIC
3D-IC
Add Route Routing Standard Cells
advanced node
analog
ARM
Azuro
cadence
Cadence Online Support
ccopt
CDN Live
CDNlive
CDNLive!
clock concurrent optimization
clocks
common power format
Conformal
Cortex-A15
Cortex-A9
Cortex-M0
CPF
DAC
dbGet
design rules
DFM
Digital
Digital Implementaion
Digital Implementation
Double Patterning
ECO
ECOs
ecounter
EDI
EDI 10.1
EDI 11
EDI 11.1
EDI system
Encounter Digital Implementation
encounter digital implementation system
Encounter Digital Implementation System 8.1
Encounter Test
ETS
extraction
five minute
five minute tutorial
five-minute
floorplanning
GlobalFoundries
hierarchical design
IBM
Industry Insights
IP
LEF
lithography
Logic Design
low power
low-power
low-power design
mixed signal
mixed signal design
Mixed signal physical implementation
mixed-signal
NanoRoute
nanoroute encounter routing
oa
OA flow
open access
OpenAccess
parasitics
placeDesign
placement
power
power analysis
Power Routing using Encounter
POWR RING
puzzler
QRC
routing
RTL compiler
signal integrity
silicon realization
SOC
SOI
STA
static timing analysis
synthesis
tcl
test
TSMC
TSV
tutorial
Virtuoso
webinar
ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow
For several years, ARM has offered processor optimization utilities (called POPs) that help users of ARM Cortex-A series processors optimize power, performance and area for a given process. This week (Aug. 9) ARM and Cadence took things one step further by announcing a POP that includes scripts that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 9 2012
Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New Signoff Approach
In the semiconductor design flow, engineering change orders (ECOs) are as inevitable as death and taxes. While this has always been the case, ECO timing closure is becoming increasingly difficult as the number of operating modes and process-voltage- temperature (PVT) corners skyrockets. What's needed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 6 2012
In Case You Missed It – The Most Popular EDI System Knowledge Content Published in Recent Months
I mentioned in my first blog one of my roles in customer support is to identify and author knowledge content for Cadence Online Support ( http://support.cadence.com ). In this blog post I want to highlight some of the popular Encounter Design Implementation (EDI) System content published in recent months...
Posted to
Digital Implementation
(Weblog)
by
wally1
on Mon, Aug 6 2012
Technology File Modification Issues / Encounter Prevent ViaCell Generation
We are using the IBM cmrf8sf PDK. We have designed a standard cell library, but we were not able to import this into Abstract Generator because it lacked required metal spacing. To remedy this, we dumped the cmrf8sf techfile, added the required spacings, compiled it and attached to a library copy, and...
Posted to
Digital Implementation
(Forum)
by
bsparkma
on Tue, Jul 31 2012
How to dump out blockages into a file
Hi all, I want to dump out placement blockage (hard,soft,partial) into file is there any utility in encounter gui to do so,as we can do to dump out the marco place,By using save "place" utility in gui and vice versa to dump routing blockages. So can any one guide me if there's any utility...
Posted to
Digital Implementation
(Forum)
by
Anuragjn
on Tue, Jul 31 2012
DFM issues
Dear Brian Hope you are doing fine and well , I would just like to learn a few more tips (with your help of course). 1. I am trying to put multiple vias on metal contacts. 2. I also want to increase the width of the metal wires by defining a "Non-Default-Rule" in the encounter tool . Both these...
Posted to
Digital Implementation
(Forum)
by
BraveHeart
on Sat, Jul 28 2012
10 Encounter Tips and Tricks You May Not Be Aware Of
In looking over the shoulders of Encounter users over the years I've found there's a bunch of little tips and tricks I use to make interacting with the tool a little easier that aren't necessarily immediately obvious. Here are some of the more common ones I used this week: When navigating...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Fri, Jul 27 2012
Encounter Antenna Diode Cells and Filler Cells causing Short Errors
I am trying to do P&R on a design, but it seems that all of my antenna diodes and filler cells cause short errors to the vdd and gnd rails in Encounter using Verify Geometry after placement. The filler cell is only two metal rails in the same locations as our standard cells (labelled correctly for...
Posted to
Digital Implementation
(Forum)
by
bsparkma
on Thu, Jul 26 2012
Synthsis of VHDL-2008 on RC
Dear All, I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly. However, I am not able to synthesis the same code using RC. I am using Cadence 5 flow with RC v10.1. What is your recommendations to overcome this issue...
Posted to
Digital Implementation
(Forum)
by
shahein
on Thu, Jul 26 2012
Capturing and Processing Encounter Console Output with "redirect"
In my last post I wrote about writing more compact db access scripts with dbGet's expression-based matching . We found all of the high fanout nets in the design which weren't clock nets: dbGet [dbGet top.nets {.numInputTerms > 16 && .isClock == 0}].name This writes the name of each...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Mon, Jul 23 2012
Page 5 of 25 (250 items)
« First
...
< Previous
3
4
5
6
7
Next >
...
Last »