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User Experience: Optimizing Power and Area With Formal Verification
Formal verification can be a powerful tool for low-power design optimization, according to a paper authored by Cadence and Freescale and presented at the recent DVCon conference. The paper showed how formal property checking can validate whether retention flip-flops are controllable, and identify those...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 17 2011
A Modest Proposal: Using Formal to Close Coverage Gaps
In my last blog post , I summarized some of our activities at DVCon and mentioned briefly the "Birds of a Feather" (BoF) panel and discussion on "Strategies in Verification for Random Test Generation: New Techniques and Technologies" held Monday evening. Today I'd like to fill...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Fri, Mar 11 2011
DVCon Wrap-Up and Blog Review
The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs
Digital designers and verification engineers are reaping great benefits from assertion-based verification. Why should analog/mixed-signal designers be left out? A Cadence paper presented at the recent DVCon conference showed how assertions can be applied to the analog/mixed-signal world as well. The...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
Video: SystemC Update From OSCI Chair Eric Lish
Eric Lish, manager of virtual platforms at Intel's Technology and Manufacturing Group, has been chair of the Open SystemC Initiative ( OSCI ) since October 2009. At the North American SystemC User Group ( NASCUG ) meeting at the DVCon conference Feb. 28, I had the opportunity to do a brief video...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 9 2011
Video: Optimizing Area and Power Using Formal Methods
At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV). Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Mar 8 2011
Video: New Cadence Verification IP Catalog (With Denali Inside!)
Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news in verification IP that bears repeating. Specifically, last week Cadence announced a new Verification IP ("VIP") Catalog -- a complete combination of standards-based Cadence and ex-Denali verification IP, supporting...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Mar 8 2011
TLM 2.0, UVM 1.0 and Functional Verification
The DVCon 2011 conference was held this week and the Accellera Universal Verification Methodology (UVM) 1.0 release is breaking records in term of interest and attendance. UVM 1.0 is a big deal(!) The core functionality is solid and ready for deployment. Accellera held a full day tutorial on UVM 1.0...
Posted to
Functional Verification
(Weblog)
by
Sharon
on Mon, Mar 7 2011
DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs
If you want to know how challenging mixed-signal verification really is, the best thing is to listen to the people in the trenches. A March 3 lunch panel at the DVCon conference, sponsored by Cadence, allowed an attentive audience to do just that. The panel included three users and two vendor representatives...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 6 2011
DVCon? Are You Sure It's Not UVMCon or MSVCon?
As I write this, I've just returned from the most important conference and tradeshow of the year for functional verification: DVCon in San Jose. The "DV" officially stands for "Design and Verification" but most people think that it means "Design Verification" since the...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Fri, Mar 4 2011
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