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Cadence

  • GTC Panel: Getting Best Use From Older IC Process Nodes

    Time for a mainstream revolution? That was the title of a lively panel discussion at the Global Technology Conference ( GTC ) Aug. 30. Panelists noted that there's still a lot of activity at 65nm and above. They discussed why this is true, whether mature nodes can be retrofitted with new capabilities...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 5 2011
  • GTC Panel: CEOs Navigate a Changing IC Ecosystem

    Semiconductor and system design have never been more promising -- or more challenging. How can IC design companies find their way to sucess? At the Global Technology Conference (GTC) Aug. 30, three CEOs and one vice president gave their perspectives on the rapidly changing IC design and manufacturing...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 1 2011
  • Cadence crash !

    Hi, I have just installed a new PDK on my CADENCE IC 6.1.4, and I have the following errors that I cannot solve! : 1/ When I launch cadence IC6.1.4 with the command: "virtuoso", I can see in the CIW window that the initialization runs a lot of time and finally ends with : " * Error * unknown...
    Posted to Custom IC Design (Forum) by lraf on Fri, Aug 26 2011
  • Searching in the database of the cellview

    When a pin connected to a block but by net name (as seen in the test case where test<1:4> connected to Dig_top), I can't find the pin name by searching inside the data base of the block, for example: In the attached test case When I search in the data base of the cellview->Dig_top for the...
    Posted to Custom IC SKILL (Forum) by dell1 on Tue, Aug 16 2011
  • How Imec and Cadence “Wrapped Up” 3D-IC Test

    One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 1 2011
  • 8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

    It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
    Posted to Logic Design (Weblog) by David Stratman on Mon, Jun 20 2011
  • DAC Panel Calls Off “Battle” Between Prototyping and Emulation

    A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 14 2011
  • Encounter Library Characterizer alf2vhdl problem

    I used ELC to characterize a standard cell library, and used the alf2vhdl tool to generate the vhdl VITAL timing file for the library. For some reason, the VHDL format written out by alf2vhdl is not compatible with Ambit, which I need to use to synthesize a design. There doesnt seem to be an option for...
    Posted to Digital Implementation (Forum) by eklikeroomys on Tue, May 31 2011
  • Problem in layout with new cadence

    Hello, I am using the new cadence for the first time (IC6.1.5)and I am having a lot of problems with the layout (layout Suite L licence). One of the issues is that every time I create a new path. Once it is drawn, I cannot change its properties. Example: I create a M1 path of 0.5u width and I want to...
    Posted to Custom IC Design (Forum) by MariaOtz on Wed, May 4 2011
  • Cadence System Development Suite – The Story is the Continuum

    Cadence today (May 3) is introducting the System Development Suite , a set of four connected platforms that support hardware/software co-development from the architectural level through final prototyping. The story is not just that Cadence now has solutions for virtual prototyping and FPGA prototyping...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 3 2011
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