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3D-IC

  • Cadence SiP and IC Packaging at DesignCon

    Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI. This integration not only supports signal integrity, but also there is new package power integrity technology. We will also be showing techniques where Package-on-Package...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Fri, Jan 23 2009
  • CDNLive! - 10 Gbit package design paper available to conference attendees

    For those of you that attended CDNLive! but may have missed the presentation on multi-gigabit package design by Kevin Roselle of Bayside Design, you can review the slide presentation by using your conference login and then downloading from here . Bayside is involved in designing many high-end packages...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Wed, Oct 1 2008
  • TSV, mainstream or niche?

    I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization. I have heard several companies (foundries and some iDM's) talking about pilot projects...
    Posted to IC Packaging and SiP (Weblog) by SiPper on Wed, Sep 24 2008
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