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3D-IC

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3D IC Ecosystem Panel: Different Views, Challenging Questions

The 3D IC supply chain ecosystem is just beginning to emerge, with roles that are currently unclear. So what happens when you bring together representatives from an outsourced assembly and test (OSAT) provider, memory maker, foundry, EDA vendor (Cadence), and a customer? The result: differing perspectives...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 3 2011
Wide I/O Memory and 3D ICs – A New Dimension for Mobile Devices

There's a lot of excitement about 3D ICs with through-silicon vias (TSVs), and one reason is that stacked die can provide very fast memory access. That's why wide I/O is emerging as a significant new direction for 3D ICs - and why the March 28 Cadence announcement of the first wide I/O memory...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 28 2011
Q&A: What Designers are Finding at 28nm – and How a “Unified” Digital Flow Can Help

Early adopters are starting to design at 28nm and are running into some challenges, according to Rahul Deokar, product management director for digital Silicon Realization at Cadence. In this interview he talks about challenges designers are experiencing due to design rules, lithography, low power, mixed...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 16 2011
Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow

It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the semiconductor industry?" If the latter is your...

Posted to Digital Implementation (Weblog) by Design4Life on Mon, Jan 31 2011
New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification across the digital, analog, and packaging domains. It's part of a larger announcement of a digital end-to-end flow. What follows are some more details on...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 31 2011
Whitepaper: 3D ICs Pose Design Challenges, But No “Showstoppers”

3D ICs with through-silicon vias (TSVs) promise tremendous power, cost, and size advantages, but they also generate a lot of concern about what's required in terms of design flows, skills, and tools. A new Cadence whitepaper ( click here to read ) sets the record straight by taking a balanced look...

Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 7 2010
Favorite Features of an IC Package Designer: Wirebonding

This is the fourth in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. While wirebond packages are nothing new, the challenges associated with package designs using wirebonds have continued to grow. Stacking die...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Mon, Nov 8 2010
3D-IC TSV Realization: The Race Has Begun!

3D IC discussions are creating quite a buzz these days. No conference is complete without a mention of 3D ICs, and there are reasons behind that. 3D ICs using through-silicon vias (TSVs) help you meet challenging performance and power targets to serve the growing demands of the networking, graphics,...

Posted to Digital Implementation (Weblog) by samtabansal on Tue, Oct 12 2010
Favorite Features Of An IC Package Designer: Assembly Rule Checks

This is the third in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool. As the industry continues to include larger numbers of larger die in a smaller IC package, the question of "Can this be manufactured?"...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Wed, Jul 28 2010
Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats

This is the second in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. Recently on a visit to an avid user of IC Package design tools, we heard the requirement mantra of efficiency and flexibility. Many package designers...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Thu, May 20 2010

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3D-IC

3D IC Ecosystem Panel: Different Views, Challenging Questions

Wide I/O Memory and 3D ICs – A New Dimension for Mobile Devices

Q&A: What Designers are Finding at 28nm – and How a “Unified” Digital Flow Can Help

Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow

New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

Whitepaper: 3D ICs Pose Design Challenges, But No “Showstoppers”

Favorite Features of an IC Package Designer: Wirebonding

3D-IC TSV Realization: The Race Has Begun!

Favorite Features Of An IC Package Designer: Assembly Rule Checks

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats