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Xiuya Li

Mr. Xiuya Li is Staff Product Engineer for Analog/Mixed Signal product, specifically for Digital Mixed Signal (DMS) and AMS-Spectre/AMSAPS. Xiuya has been Sales Technical Leader (FAE) in Custom IC group, Technical Field Operations, Cadence Design Systems, Inc. As a pre-sales application engineer, Xiuya supported Analog, Mixed Signal and RF design flow in Cadence Virtuoso Custom Design Platform, including Composer, Analog Design Environment (ADE), Spectre/RF, APS, Ultrasim, AMS Designer, and behavioral modeling with Verilog, VHDL, VerilogA and Verilog AMS. Xiuya has been working in Cadence since Jan. 2002. Prior to Cadence, Xiuya has been an electronics design engineer for 5 years in P.R. China, Republic of Singapore and United States, and he has 2 years’ teaching experience in Electronics Teaching and Research Group in Tsinghua University, Beijing, P. R. China. Xiuya holds BSEE and MSEE degrees from Automation Department in Tsinghua University. He also holds a Master’s Degree in Electrical Engineering from University of Wisconsin – Milwaukee.

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Behavioral Model Validation with amsDmv
By Xiuya Li on November 30, 2011 a msDmv (Analog Mixed Signal Design and Model Validation) is an application integrated in the Cadence Virtuoso GUI flow and it can also be invoked from command line with some feature limitations. amsDmv can be used to compare the simulation restults and   Read More »
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