Home > Community > Blogs > Bloggers > Timothy Pylant
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Share
  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Blogger

Timothy Pylant

I started my career in 1984 doing board design for F-16 avionics and then moved to Compaq Computer in 1988 where I supported the use of design and verification tools for ASIC development. In 1992, I joined Cadence to continue that role as an Applications Engineer. I am currently working in the Design and Verification Core Comp team in support of SystemVerilog, assertion-based, and low-power verification. I have also published several papers in these areas and been a reviewer for SystemVerilog for Verification and Step-by-Step Functional Verification with SystemVerilog and OVM.

View Member Profile »
Create a Sine Wave Generator Using SystemVerilog
By Timothy Pylant on June 30, 2009 Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI. Obviously, to produce a sine wave, you need access to the sin function. This   Read More »
Comments (5)
View older posts »