Home > Community > Blogs > Bloggers > Team Specman
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


Team Specman

The "Team Specman" blogging core team is:

View Member Profile »
Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components
What happens when you have two verification components (for example one implemented in e and the other in System Verilog) and one of the frameworks drops its last TEST_DONE objection?   Read More »
Comments (0)
Implementing User-Defined Register Access Policies with vr_ad and IPXACT
The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it   Read More »
Comments (0)
Updates from the UVM Multi-Language (ML) Front
An updated version of the UMV-ML Open Architecture library is now available on the Accellera uploads page (you need to login in order to download any of the contributions). The main updates of version 1.4 are: UVM-SV library upgrade: This release includes   Read More »
Comments (0)
sync and wait Actions vs. Temporal Struct and Unit Members
Using sync on a temporal expression (TE), does not guarantee that the execution will continue whenever the TE seems to succeed. In this example, the sync action will miss every second change of my_event: tcm0()@any is { wait; while TRUE { sync change   Read More »
Comments (0)
Applying Software-Driven Development Techniques to Testbench Development
Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow customers to validate their testbench in isolation   Read More »
Comments (0)
Randomizing Error Locations in a 2D Array
A design team at a customer of mine started out with Specman for the first time, having dabbled with a bit of SystemVerilog. I can't reveal any details of their design, but suffice to say they had a fun and not-so-simple challenge for me, the outcome   Read More »
Comments (0)
e Language Editing with Emacs
Specman and e have been around for a while, and some clever people have developed a nice syntax highlighting package for Emacs. What does this package do? Well, have a look yourself: Editing in Emacs with the Specman mode And Editing in Emacs without   Read More »
Comments (0)
Covering Edges (part II)—“Inverse Normal” Distribution
In the previous example , we used the "select edge" to generate edge values for fields. But in many cases, what you really want to generate is not the exact edge, but "near the edges". For example, for a field of type uint (bits :   Read More »
Comments (0)
Generic dynamic run-time operations with e reflection Part II
Field access and method invocations In the previous blog , we explained what are untyped variables and value holders in e , and how to assign and retrieve values to/from them. In this and the next blogs, we will see how they can be used in conjunction   Read More »
Comments (0)
Covering Edges (Part I) – Cool Automation
With random generation, most of the fields are due to be quite well covered. If the field is of a type with a wide space, e.g. address is of 32 bits, then most likely not each and every of the 0xffffffff values will be generated. As verification engineers   Read More »
Comments (0)
View older posts »