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Team Allegro

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DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques
The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied   Read More »
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OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda .) Track 6, IC Packaging/SI, PI, featured customer papers on co-design as well as signal and   Read More »
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Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2014
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here . Track 6, the IC Packaging/SI, PI featured customer papers on co-design as well   Read More »
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Multi-Fabric Planning for Efficient PCB Design
Recently, an article was published in Printed Circuit Design and Fab by Cadence product manager Kevin Rinebold talking about Multi-Fabric Planning for Efficient PCB Design (see page 22 of printed magazine). Today's BGA-style packages have a significant   Read More »
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Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity
How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting   Read More »
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Signal Integrity Analysis of Serial Data Channels—A Complete Solution Using Allegro Sigrity
Back in the day, when challenged to transfer data faster, we increased the width of the interface from 8 bits to 16 or from 16 to 32 and so on. The wider the bus got, the more challenging timing became. We added strobes for interface lanes to better manage   Read More »
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Why Does Signal Integrity Analysis Need to be Power Aware?
Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec, there has been a lot of buzz in the industry   Read More »
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Power Integrity Solution Spans Multiple PCBs and Packages
When designing next-generation products, the common theme is "faster, smaller, cheaper". When that is combined with longer battery life and lower power consumption requirements, the design challenges can be daunting. And one thing you know for   Read More »
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Bending a Few IC Package Design Rules – With Confidence
Somewhere out there is an IC package designer who has been given design guidelines and cannot possibly meet the maximum layer constraints. You probably know this guy or gal (let's call her a gal). What is she supposed to do? Should she increase the   Read More »
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Simultaneous Switching Noise Analysis – The Earlier the Better
The evolution of signal integrity analysis is similar to many electronic design tasks. First, best practices were followed. Second, analysis tools were used to verify final designs. Then, to reduce design re-spins, what-if analysis techniques were created   Read More »
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