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Blogger

Sumeet Aggarwal

I have been working in EDA since 2000. After supporting Cadence customers on Functional Verification Platform for initial 11 years, I moved to Cadence Online Support where my job is to ensure we have good collateral and self-help content on Functional Verification, System Design and Verification, Front-End Design and IP technologies and tools.

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How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your Desk?
The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly   Read More »
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Learn Logic built-in self-test (LBIST) macro generation and insertion at your desk
Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.   Read More »
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Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support in Q1 2014
In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and technologies. In this second quarterly blog, let me   Read More »
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RTL Compiler (RC) Timing Analyzer (RTA) Flow
The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was   Read More »
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Incisive Verification: Top 10 Things I Learned While Browsing Cadence Online Support Recently
There is always a demand, in most corners of the world today, for learning and troubleshooting something simply and quickly. Most users of any product or tool want access to a self-service knowledge base so that they can go and troubleshoot the issue   Read More »
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New Rapid Adoption Kit on Encounter RTL Compiler: RC-Physical Low Power Flow
Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows   Read More »
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Encounter® RTL Compiler Hierarchical ILM (Interface Logic Model) Flow
How to use Encounter® RTL Compiler support Interface Logic Models during synthesis.   Read More »
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Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit
Code coverage is an effective tool in the verification process, giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time-consuming   Read More »
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RTL Compiler Beginner’s Guides Available on Cadence Online Support
With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences   Read More »
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Accelerated Code and Functional Coverage Using Palladium XP
Code coverage is an effective tool in the verification process—giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time   Read More »
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