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Richard Goering

I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.

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Sean Dart Q&A: Former Forte CEO Discusses Past, Present, and Future of High-Level Synthesis
Earlier this year Cadence acquired Forte Design Systems , a pioneer of high-level synthesis (HLS) and provider of the Cynthesizer SystemC-based synthesis tool. Sean Dart, Forte CEO since 2006, is now senior group director for R&D at the Cadence System   Read More »
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Protium FPGA-Based Prototyping Platform – Speeding Bring-Up Times
FPGA-based prototypes provide excellent platforms for pre-silicon software development - but prototype bring-up times are so long and painful that much of the value is lost. Promising to shorten bring-up times by up to 70% versus competing commercial   Read More »
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Quantus QRC Extraction Solution – Massive Parallelism Extracts Accurate Parasitics Quickly
Over the past 14 months Cadence has brought massive parallelism to static timing analysis ( Tempus Timing Signoff Solution ) and power analysis ( Voltus IC Power Integrity Solution ). Today (July 14, 2014) Cadence is announcing the Cadence Quantus QRC   Read More »
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IP Talks! Keynote at DAC 2014—Rethinking Image Processing in SoC Design
Many systems on chip (SoCs) have a "camera block" or image signal processor (ISP) that takes raw data from an image sensor and manipulates that data. But ISPs are moving away from their traditional role and turning into "vision subsystems   Read More »
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DAC 2014 Panel: FinFET IC Design Poses No Roadblocks, but Lots of Details
FinFET transistors promise enormous power and performance advantages at process nodes below 20nm, but how will they impact IC design? If you're a digital designer, not much changes - but if you're a custom/analog designer, there's a lot to   Read More »
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DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com
One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed   Read More »
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DAC 2014: High-Level Synthesis (HLS) Users Share Advantages, Challenges
High-level synthesis (HLS) is an emerging IC design technology that promises huge productivity gains, but you need to understand its advantages and limitations before diving in. The best way to get that understanding is to listen to the experiences of   Read More »
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China Fabless Semiconductor Panel: Don’t Pack Your Bags Just Yet
Has the center of gravity for system on chip (SoC) innovation shifted to China? If you're planning to start a fabless semiconductor company, should you pack your bags, leave Silicon Valley, and head for Shenzhen or Shanghai? Not so fast, according   Read More »
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Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM
The Universal Verification Methodology ( UVM ) has compelling advantages for IC verification but can be challenging to adopt, according to panelists from four user companies at an Accellera breakfast at the recent Design Automation Conference (DAC 2014   Read More »
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Why Cadence Bought Jasper—a New Era in Formal Analysis
Cadence today (June 16, 2014) announced the completion of its acquisition of Jasper Design Automation , a leading provider and pioneer of formal analysis and verification tools for IP and system-on-chip (SoC) development. The acquisition allows Cadence   Read More »
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