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Richard Goering

I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.

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IEEE Working Groups Open New Frontiers in Low-Power Design
For many years, electronic designers have struggled to produce low-power chips and systems with tools and standards that focus on register-transfer level (RTL) hardware. After much talk about taking power optimization to higher levels of abstraction,   Read More »
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DVCon Europe 2014—A “First” for Munich, Oct. 14-15
For over 20 years, DVCon (Design and Verification Conference) has been a premier Silicon Valley event for functional IC design and verification. In 2014, for the first time, DVCon is going overseas—for DVCon Europe on Oct. 14-15, as well as DVCon   Read More »
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Archived Webinar: Cadence, ARM Forge Design Flow for Mixed-Signal Internet of Things (IoT) SoCs
Many people talk about the Internet of Things (IoT) and how it will affect our work, health, leisure time, communications, and more. As a recently archived webinar shows, Cadence and ARM have gone beyond mere talk and have developed an integrated design   Read More »
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Q&A: From Customer to R&D Director of FPGA-Based Prototyping
Vahid Ordoubadian, senior group R&D director at Cadence, has a unique perspective when it comes to emulation and FPGA-based prototyping—he was a user of these technologies for many years. In early 2014, he left Broadcom and joined Cadence, where   Read More »
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PCB West 2014: IPC-2581 Data Transfer Format Links Design, Manufacturing
IPC-2581 is rapidly gaining support in the PCB design community as an "intelligent," vendor-neutral format that can bring design data into manufacturing in a single file. The PCB West conference in Santa Clara, California on Sept. 10, 2014 provided   Read More »
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Cadence at ARM TechCon 2014—High Performance, Low Power, Mixed Signal, and More
ARM TechCon 2014, set for October 1 – 3 in Santa Clara, California, is a key event for anyone who designs or programs ARM®-based systems-on-chip (SoCs). Cadence has a strong presence this year with five sponsored sessions, three technical papers   Read More »
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Report Envisions Bold New Future for EDA
A series of workshops on "Extreme Scale Design Automation" has resulted in a report that identifies EDA research and funding priorities through 2025 and beyond. The report cites today's challenges and shortcomings, but it also envisions   Read More »
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Electromigration – What IC Designers Need to Know
If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety system). That's why reliability is so important in   Read More »
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IBM Lithography Expert: Making 10nm IC Design Possible
Development work is underway on the 10nm process node - but can we get there with conventional lithography? In a recorded presentation available at the Cadence web site, Lars Liebmann, distinguished engineer at IBM, says yes - but he notes that it will   Read More »
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3D-IC Working Group—Tool Support Needed, But “Gaps” May Be Narrowing
Where are the gaps in 3D-IC design, and how can they best be bridged? In order to provide a cost-effective alternative to silicon process scaling, work is still needed in 3D-IC design tools and methodologies, according to presenters at a recent meeting   Read More »
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