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Blogger

Richard Goering

I've been writing about EDA and IC design for 25 years. I've worked as an editor for Computer Design, EE Times, and SCDsource. I now work at Cadence as senior manager of technical communications, and I manage the Industry Insights blog.

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Panelists: Bridging the Gap Between Analog and Digital Design
Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow   Read More »
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Whitepaper: Verification Performance is More Than Raw Simulation Speed
RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises   Read More »
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Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore   Read More »
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SPIE Papers Showcase DFM and Lithography R&D
Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational   Read More »
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Webinar Report: Power-Aware Mixed-Signal Verification
Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption   Read More »
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Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic   Read More »
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Webinar Report – New Approaches to Mixed-Signal Verification and Assertions
Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between   Read More »
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“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams   Read More »
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Update on OrCAD Free and Paid “Apps” – What is Available Now
Last year Cadence announced the OrCAD Capture Marketplace , a web-based capability within the OrCAD Capture environment that provides an on-line store with free and paid plug-in tools, or "apps." Since then the list of available apps for OrCAD   Read More »
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CDNLive! Silicon Valley – Agenda Set, Registration Open, $99 Deal
CDNLive! Silicon Valley, the Cadence user conference for the U.S., is set for San Jose, California March 13-14 at the DoubleTree Hotel. An agenda and registration information are now available on line , and there's a special "early bird"   Read More »
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