IBM/Cadence Collaboration Points To “Next Generation” EDA
By
Richard Goering
on
February 8, 2010
Embedded software development and hardware/software integration have become primary bottlenecks for system-on-chip (SoC) projects. Still, most EDA tools remain exclusively focused on hardware design, while software development tools have no understanding
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DesignCon Panel: “Total” IP Solutions Fuel SoC Integration
By
Richard Goering
on
February 5, 2010
Panelists at DesignCon Feb. 3 agreed that just shipping RTL code for silicon IP is far from sufficient. But what comprises a “total” IP solution for SoC integration? That’s a little more complicated, and it fueled a good discussion with
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Apple A4: What We’ve Heard, What We Can Learn
By
Richard Goering
on
February 3, 2010
The big mystery behind the recent Apple iPad announcement is the A4 processor that powers this touchscreen, “tablet” PC. What’s in it, and why did Apple design its own system-on-chip (SoC) as opposed to using off-the-shelf hardware?
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Intel Speaker: How to Avoid “Firefighting” in Verification
By
Richard Goering
on
February 1, 2010
Can verification engineers gain control over the verification process, and stop being full-time firefighters? With proper planning, communication, and organization, the answer is “yes,” according to Allison Goodman, validation program manager
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Why Twitter Is Useful For #EDA
By
Richard Goering
on
January 28, 2010
When Twitter first came out, I couldn’t figure out how it could possibly be useful in a professional setting. What can you say in 140 characters or less? “Going to cafeteria for lunch now – thoughts?” It seemed like a restrictive
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Guest Blog: Making Restricted Design Rules Work
By
Richard Goering
on
January 27, 2010
Applying restricted design rules (RDRs) to conventional design styles won’t produce good results, says Scott Becker, CEO of Tela Innovations. A better approach, he says, is to start with a restricted design style with regular layout patterns. There’s
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Analog Simulation – Looking Beyond “Wall Clock” Time
By
Richard Goering
on
January 25, 2010
The primary way that people describe or categorize analog simulators is in terms of raw performance – what one might call “wall clock” time. That’s a short-sighted view. The real issue is verification productivity, and that’s
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Should IC Designers Worry About Temperature?
By
Richard Goering
on
January 21, 2010
Three years ago I wrote an EE Times article about the growing importance of thermal gradients and thermal analysis at 90 nm and below. That article turned out to be ahead of its time. Today, thermal issues are not among the top few designer concerns at
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A Visit To Cadence Research Labs, Part 2
By
Richard Goering
on
January 20, 2010
As noted in part one of this blog series, the Cadence Research Laboratories in Berkeley, California is a unique EDA research organization that has contributed to a number of products and technologies in IC and systems design. What really makes the lab
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A Visit To Cadence Research Labs, Part 1
By
Richard Goering
on
January 18, 2010
Located a block away from the University of California at Berkeley, the Cadence Research Laboratories provides a unique environment for EDA innovation. But what really goes on there, who works there, and what is the place like? To find out, I recently
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