User Interview: How ECO Handling Works With Equivalence Checking
By
Richard Goering
on
November 19, 2009
Vishvabhusan Pati is a senior staff engineer and manager at Qualcomm , where he’s involved in design work and formal and semi-formal design verification. In this Q&A interview, he discusses advantages and limitations of formal equivalence checking
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Guest Blog: Characterizing Process Variability At 32 nm And Below
By
Richard Goering
on
November 18, 2009
Process characterization becomes much more complex as feature sizes shrink. In this guest blog Jim Bordelon, president and CTO of Stratosphere Solutions , describes requirements and methodologies for modeling variability at 32 nm and below. Peering under
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User Panel: Can Formal Tools Reduce Need For Simulation?
By
Richard Goering
on
November 16, 2009
It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort
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User Interview: Formal Analysis Speeds IP Connectivity Verification
By
Richard Goering
on
November 12, 2009
The biggest challenge with verification is “always the schedule,” according to Chaitanya Kosaraju, senior design engineer at Xilinx . Thus, anything that can cut verification time without compromising coverage presents a huge advantage. At
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Panel Question: Should Designers Do Their Own Verification?
By
Richard Goering
on
November 11, 2009
One question that prompted a lively discussion at the recent Cadence Mixed-Signal Design Summit was whether design engineers should do their own verification. This is a particularly good question for analog and mixed-signal design, where the tradition
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“Software Signoff” Raises Many Questions
By
Richard Goering
on
November 9, 2009
At a discussion at the ICCAD conference last week, EDA notables Jim Hogan and Paul McLellan talked about “ what EDA needs to change for 2020 success. ” One topic they emphasized is “software signoff,” and they encouraged those
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DFT Challenge: Evaluating The True Cost Of Test
By
Richard Goering
on
November 5, 2009
Remember DFT? “Design For Test” faded into the background in recent years as the industry turned its focus to DFM, but if anything test is an even larger concern than it was 10 or 15 years ago. That’s because test is becoming more difficult
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Greatest Moments In EDA Innovation
By
Richard Goering
on
November 3, 2009
Innovation is the lifeblood of the EDA industry, and it is only because of innovation from many sources – including academia and industry – that modern IC design is possible at all. Today at Cadence (Nov. 3, 2009), we are celebrating Cadence
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Users Outline New Approaches To Mixed-Signal Verification
By
Richard Goering
on
November 2, 2009
At the Cadence Mixed-Signal Design Summit , held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are
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User Interview: How To Estimate Power Early
By
Richard Goering
on
October 29, 2009
Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology ( IDT ). At the recent CDNLive! Silicon Valley , he presented a case study of architectural
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