SystemC AMS – A New Proposal For Mixed-Signal Verification
By
Richard Goering
on
March 18, 2010
In an effort driven by European semiconductor companies and universities, the Open SystemC Initiative ( OSCI ) last week announced the first version of the SystemC analog/mixed-signal language standard, AMS 1.0. Since Cadence is the industry leader in
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ARM AMBA 4 Protocol And VIP – A Closer Look
By
Richard Goering
on
March 17, 2010
ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's
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Bringing MEMS Design To The Mainstream
By
Richard Goering
on
March 15, 2010
Micro-electrical mechanical systems ( MEMS ) have been around for years, and have found their way into high-volume applications such as automobile air bag controllers, GPS systems, and inkjet print heads. But MEMS devices such as accelerometers, gyroscopes
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Challenging Misconceptions About Verification Languages
By
Richard Goering
on
March 10, 2010
One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way
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Q&A: New Challenges, New Solutions In IC Implementation
By
Richard Goering
on
March 8, 2010
Advanced nodes are raising tough new challenges for analog/mixed-signal and digital IC implementation, according to David Desharnais, group director and product manager for implementation at Cadence. In this interview, he notes where IC designers are
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DVCon OVM Panelists: Easing The Debug Challenge
By
Richard Goering
on
March 4, 2010
The good news about the Open Verification Methodology ( OVM ) and the advanced verification techniques it supports is that verification engineers are now finding more bugs than ever. The bad news is that the bottleneck is shifting to debugging. What are
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DVCon Panel: Three Ways To Minimize Verification Effort
By
Richard Goering
on
March 2, 2010
With verification taking up more and more of the design cycle, is there any hope that verification will keep up with escalating design complexity? Yes, according to panelists at the DVCon conference Thursday Feb. 25. From the discussion, I distilled three
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DVCon Panel: Why Verification Engineers Are “Sleepless”
By
Richard Goering
on
March 1, 2010
I view a panel as successful when I leave the room knowing more than when I came in. Such was the case at the "What keeps you up at night" panel at DVCon Feb. 24, which offered some interesting, provocative, and in several cases surprising perspectives
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Lip-Bu Tan Keynote: Rethinking EDA For 2010 And Beyond
By
Richard Goering
on
February 25, 2010
Business conditions are looking up for the EDA and semiconductor industries, but customer concerns have shifted, according to Lip-Bu Tan, president and CEO of Cadence. At a DVCon keynote speech Feb. 24, Lip-Bu described a new landscape in which EDA providers
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DVCon SystemC Day Quandry: Need for Third Party TLM IP
By
Richard Goering
on
February 24, 2010
Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was
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