Is Equivalence Checking a MUST for signing off an FPGA netlist targeting very large FPGA Devices?
By
Bassilios Petrakis
on
September 19, 2008
The majority of designers today use equivalence checking for netlist signoff prior to tapeout or ASIC vendor netlist handoff. As FPGA devices become larger and larger capable of tens of millions of gates, will equivalence checking become the norm rather
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