Low-Power Design? Brian Bailey Gets It
By
Pete Hardee
on
May 2, 2012
Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles
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Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
By
Pete Hardee
on
March 7, 2012
CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification
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Does Substrate Biasing Have a Future?
By
Pete Hardee
on
February 6, 2012
At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive
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Low Power Design in 2011 and Predictions for 2012
By
Pete Hardee
on
December 22, 2011
It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward
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Low Power Marketing Hype – And What They Don’t Tell You
By
Pete Hardee
on
November 30, 2011
Here in the USA, we're just back from the Thanksgiving holiday. This year, I got caught up in "Black Friday," which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I'm
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Cadence Low Power Guru Wins Si2’s Distinguished Service Award
By
Pete Hardee
on
October 21, 2011
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Another Expert’s View on Power Intent and Hierarchy
By
Pete Hardee
on
September 21, 2011
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An Expert’s View on Power Formats and Methodology
By
Pete Hardee
on
August 24, 2011
In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress
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Low Power Design -- Alive and Well at DAC
By
Pete Hardee
on
June 14, 2011
Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing
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Report from Japan – Quake Brings New Perspective on “Power”
By
Pete Hardee
on
March 15, 2011
Back in December, I wrote a blog entry entitled " Perspective on Power - 300 Designers and 20,000 Miles Later... ". After the latest leg of my travels last week, taking our EDA360 Tech on Tour Low Power Symposium on the road to Taiwan and Japan
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