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Hemant Shah

Hemant Shah joined Cadence SPB division in late 2000 as Product Marketing Director for High-Speed Products. Prior to joining Cadence, Hemant was at Xynetix Design Systems, Inc. where he was engineering director for advanced development for 3 years and product marketing director for EDAnavigator, a virtual prototyping tool for PCB systems, for 4 years. Prior to Xynetix, he played various engineering management roles at Intergraph Corporation for 12 years including managing two remote sites in India and Israel. Development of advanced PCB design tools ranged from front end CAE tools [schematic capture, integration of third party tools for Verilog & VHDL design, logic simulation, hardware acceleration from IKOS, ZyCAD; PLD/FPGA tools from Minc, Data I/O and Synthesis tools from AT&T Bell Labs] to PCB layout tools [interactive placement and routing, automatic placement and router]. He holds a B.S. in Electrical Engineering and a M.S. in Computer Science.

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How Do You Route Your Highly Constrained PCBs? (Part 1 of 2)
How routing is performed to meet the design intent of designers and engineers seems to be a topic of constant debate. Is manual routing better than automatic routing? Is designer-guided, computer-assisted (IOW auto-interactive) better? What’s the   Read More »
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Miniaturization Through Embedding Packaged Components – Part2
This blog was written by a guest blogger – Mark Beesley of AT&S. His company is a global leader in supplying advanced interconnect solutions to the high-end electronics sector. AT&S leads HERMES, a European consortium focused on developing   Read More »
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Miniaturization Through Embedded Packaged Components
As consumers we are very familiar with product miniaturization trends. We demand more functionality in smaller sizes that have longer battery life all the time. The electronics market has been delivering to those customer expectations not just in consumer   Read More »
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Shorter, Predictable Design Cycles (SPDC) – Ensuring Critical Signals Have a Return Path
This is third in the series of blog posts about making your design cycles predictable and shorter for dense PCBs that have highly constrained high-speed interfaces such as DDR2, DDR3, SATA II/III, and USB 3.0. The first post talked about using ECSets   Read More »
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A Shorter, Predictable Design Cycle for Complex PCBs - Dynamic Phase Control
This is second in a series of blog posts about making your design cycles shorter and more predictable for increasingly complex PCB designs. In my last post I talked about using ECSets and Topology Apply capabilities for high-speed standards based interfaces   Read More »
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A Shorter, Predictable Design Cycle for Complex PCBs -- Electrical Constraint Sets (ECSets)
This is the first in a series of blogs focused on how you can make your design cycle predictable and shorter for PCB designs that are increasing in complexity. PCB designers have to deal with increased complexities while design teams are dispersed geographically   Read More »
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Innovative Approach to Optimized FPGA Pin Assignment
Cadence has been a leader in silicon-package and package-board co-design for over a decade now. Today, Cadence introduced a new and innovative solution for FPGA-PCB Co-design. The FPGA-PCB co-design solution includes proven technology from Taray Inc for   Read More »
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SPB 16.2 release - Constraint Driven HDI PCB Design Flow
Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers. I will be talking about the improvements in this release over a few   Read More »
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