Speeding up SystemC compilation with Incisive SystemC
By
George Frazier
on
June 19, 2009
If you’re a C++ and SystemC programmer you know that when you’ve spent all day tracking down a nasty bug, nothing can bum your trip more than having to wait around for a long recompile. Compile time is a bottleneck for SystemC development
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Tracing TLM 2.0 Activity in an ESL Design – Part 3
By
George Frazier
on
May 7, 2009
Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM 2.0 transaction data ( http://www.systemc.org ). In this post, we’ll explore the data in the Simvision Waveform Viewer, the Transaction Explorer, and with TxE
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Tracing TLM 2.0 Activity in an ESL Design – Part 2
By
George Frazier
on
April 7, 2009
In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in a design: using output statements to write to a text file or the terminal and using SCV transaction recording to write to a database such as SST2. If your goal is to debug
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Tracing TLM 2.0 Activity In An ESL Design – Part I
By
George Frazier
on
March 23, 2009
Many design teams that use SystemC are in various stages of evaluating TLM 2.0 – the Open SystemC Initiative’s transaction level library designed for modeling memory-mapped buses and on-chip communication networks. The new standard takes us
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SystemC Save and Restore Part 2 - Advanced Usage
By
George Frazier
on
March 9, 2009
In my last post I discussed how to use save / restore in the Cadence Incisive Simulator to create checkpoints for designs that contain SystemC. The algorithm for SystemC save / restore is fundamentally different than the algorithm for HDL designs. Although
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How to Save OS Boot Time In Your SystemC Virtual Platform With Save and Restore
By
George Frazier
on
February 18, 2009
One advantage of using a virtual platform or virtual prototype over real hardware for embedded software development and testing is the ability of some simulators to save snapshots of their state. If your processor model is detailed enough, it might take
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