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Axel Scherer

Axel Scherer is a solutions architect at Cadence Design Systems in Massachusetts, leading the Incisive Product Expert Team for testbenches in general and the Universal Verification Methodology (UVM) in particular.

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Resetting Your UVM SystemVerilog Environment in the Middle of a Test — Introducing the UVM Reset Package
A package to enable resetting a UVM environment in the middle of a test was contributed to Accellera. Its real world application will be presented at DVCon 2014 by Analog Devices.   Read More »
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Test Your Units Before Your Units Test You — Testing Your Testbench
Announcing a webinar and a DV Conpaper presentation on how to use unit testing in testbench development.   Read More »
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That Cowbell Must be Registered – Introducing the UVM SystemVerilog Register Layer Basics Video Series
Introduction of the new UVM Register Layer Basics video series for SystemVerilog (IEEE 1800)   Read More »
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Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
Udacity/Cadence MOOCs CS 348 course on Functional Hardware Verification will go live on Mar 12, 2013.   Read More »
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JBYOB (Just Bring Your Own Browser): Interactive Labs on Udacity CS348 Functional Hardware Verification – No Installation Required
Interactive coding in the web browser. Preview of the interactive features of Udacity CS348 Functional Hardware Verification course.   Read More »
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It’s Coming: Udacity CS348 Functional Hardware Verification Course Launches on March 12, 2013
Cadence' CS348 Functional Hardware Verification on Udacity.com will launch on Mar, 12, 2013.   Read More »
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Do you MOOC? Expanding Access to e (IEEE 1647) Verification Training Globally
Expansion of e IEEE1647 training access globally.   Read More »
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Speed of “Light” – My First iPhone 5 Impression
First impression. iPhone5 on launch day.   Read More »
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The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese
Announcing the completion of the UVM Basics for SystemVerilog videos series in Chinese.   Read More »
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Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus
Constrained random test generation. Infinity Minus.   Read More »
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