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Ahmed Elzeftawi

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Library "Safe Margins" -- Are They Really Saving Your Design?
Designers need to radically re-think their strategies for timing closure to get the most out of process technologies that are becoming readily available. The additional burdens of creating electrical cell views for timing, power and signal integrity,   Read More »
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CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient   Read More »
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