Home > Community > Blogs > Bloggers > Adam Sherer
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


Adam Sherer

I market the UVM, multi-language verification, and low-power simulator for Cadence, tapping 21 years of experience in verification and software engineering including roles in marketing, product management, applications engineering, and R&D. With nine Boston Marathons run on the Boston Children’s Hospital Marathon Team, I'm always ready to see who has the fastest verification on the planet!

View Member Profile »
e and SystemVerilog: The Ultimate Race
For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language   Read More »
Comments (0)
Cadence and AMD Add New UVM Multi-Language Features
The UVM Multi-Language Open Architecture open-source library was recently updated with new features. The hallmarks of this solution continue to be the ability to integrate verification components of multiple languages and methodologies at the testbench   Read More »
Comments (0)
ADI Success Verifying SoC Reset Using X-Propagation Technology - Video
Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity for verifying SoC reset. In November 2013 at CDNLive India they presented a paper detailnig the new technology they applied to reset verification and eight bugs they   Read More »
Comments (0)
Freescale Success Stepping Up to Low-Power Verification - Video
Freescale was a successful Incisive ® simulation CPF low-power user when they decided to step up their game. In November 2013, at CDNLive India, they presented a paper explaining how they improved their ability to find power-related bugs using a more   Read More »
Comments (0)
ST Microelectronics Success with IEEE 1801 / UPF Incisive Simulation - Video
ST Microelectronics reported their success with IEEE 1801 / UPF low-power simulation using Incisive Enterprise Simulator at CDNLive India in November 2013. We were able to meet with Mohit Jain just after his presentation and recorded this video that explains   Read More »
Comments (0)
IEEE 1801/UPF Tutorial from Accellera—Watch and Learn
If you weren't able to attend the 2013 DVCon, you missed out on a great IEEE 1801/UPF tutorial delivered by members of the IEEE committee. Accellera had the event recorded and that recording is now posted on the Accellera.or g website. Regardless   Read More »
Comments (0)
Practical Guide to the UVM for $15 - Virginia, There is a Santa!
Wondering what to get the verification engineer on your list? You know, the one with the zealous love of SystemVerilog and UVM? It's the Practical Guide to Adopting the UVM, Second Edition for only $15! The Practival Guide to the UVM is the most popular   Read More »
Comments (0)
Low-Power IEEE 1801 / UPF Simulation Rapid Adoption Kit Now Available
A new self-help training kit for the Incisive Enterprise Simulator's IEEE 1801 / United Power Format low-power features and its usage for design engineers   Read More »
Comments (0)
Fujitsu Gets 3x Faster Regression with Incisive Simulator and Enterprise Manager
Verification regression consumes expensive compute resources and precious project time, so any speed-up has both a technical and business impact. As announced July 17, Fujitsu was able to improve both the compute resource and project time by using Cadence   Read More »
Comments (0)
Introducing UVM Multi-Language Open Architecture
The new UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD. It uniquely integrates e , SystemVerilog, SystemC, C/C+, and other languages into a cohesive verification hierarchy   Read More »
Comments (0)
View older posts »