Where There's Smoke, There's fire in the Belly of an Aspiring Engineer
By
Adam Sherer
on
April 2, 2012
Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the
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Assertions Help Avoid Chip Melt
By
Adam Sherer
on
March 22, 2012
When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “ Avoiding Chip Melt ” article! Assertions are just
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Gentlemen, Start Your Simulation Engines
By
Adam Sherer
on
February 22, 2012
As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your
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Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
By
Adam Sherer
on
January 30, 2012
Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these
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UVM: "Everything that Can be Invented Has Been Invented" Not True!
By
Adam Sherer
on
January 26, 2012
Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with
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Holiday Idea #1: Give the Gift of UVM Knowledge
By
Adam Sherer
on
December 6, 2011
Your favorite verification engineer has been good all year. Thousands of tests run. Nights and weekends of debug. So how do reward her? Why, with UVM Training , of course! Cadence experts have trained hundreds of engineers on OVM and UVM. These trainers
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Come See How to Connect SystemVerilog and SystemC Using UVM
By
Adam Sherer
on
October 18, 2011
All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar
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Automating UVM to Tackle Insidious HW/SW Bugs
By
Adam Sherer
on
October 10, 2011
You've just sat through a 2-hour program review. The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying. Of course, the hardware and software reviews were boring. Blah, blah, blah about design trade-offs
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Low-power Keeps Gate-Level Simulation Forever Young
By
Adam Sherer
on
September 8, 2011
Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement
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OVM 2.1.2 -- Getting You Ready for UVM
By
Adam Sherer
on
May 31, 2011
Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs. Not too shabby! With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld
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