Creating SystemC TLM-2.0 Peripheral Models
By
Team ESL
on
July 14, 2011
Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time
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Understanding Latency versus Throughput
By
Team ESL
on
September 13, 2010
One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated. Suddenly, both "Systems designers"
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More Details on Post Silicon Embedded Software Verification With ISX
By
Team ESL
on
August 18, 2009
Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in Germany, to the TeamESL blog for the next installment on post-silicon embedded software verification with ISX. This post is a discussion featuring Markus and Joerg talking
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A Classification of ESL - High Level Synthesis Tools
By
Team ESL
on
August 6, 2009
These days, there is a lot of talk of what the next design methodology for Digital Systems will be and how this methodology will be the replacement of RTL Synthesis. The term ESL (Electronic System Level) is used as a general term for the new wave of
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Full System vs Sub-system Virtual Prototyping
By
Team ESL
on
August 6, 2009
There is a strong movement in the industry to move to create Virtual Prototypes of systems, prior to RTL coding. These Virtual Prototypes are being used for early software development and architectural analysis. Since there are typically many blocks in
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Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle?
By
Team ESL
on
August 5, 2009
Being a Brit, Cricket is never very far from my thoughts especially when travelling to India, the biggest cricket mad nation in the world. There is a saying in cricket that you should always think of doing what the opposition would least like, a statement
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Customer Questions About TLM-driven Design and Verification
By
Team ESL
on
July 27, 2009
In the latest blog published by Ron Wilson there were two questions about our TLM-driven design and verification solution introduction. We would like to respond to these comments here: 1. " one line of SystemC generates three lines of RTL "
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OVM Metric Driven Verification With an FPGA-based Design
By
Team ESL
on
June 17, 2009
During the last 2 years I have enjoyed the opportunity to work with the Incisive Software Extensions (ISX) with many customers. I learned a lot about software/hardware co-verification and we reached the point were we started to see beyond one’s
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Way Worse Than The Real Thing
By
Team ESL
on
May 18, 2009
This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual
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SystemC Debug: A Summary of Summary Probes
By
Team ESL
on
May 15, 2009
SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in
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