Update to the OVM Register Package
By
Team genIES
on
November 29, 2011
OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects
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Infinite Playbook for the Verification Superbowl
By
Team genIES
on
January 10, 2011
Its 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz. What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh
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Editor For OVM Field Registration Macros
By
Team genIES
on
February 22, 2010
The OVM SystemVerilog Class Library has built-in automation for many service routines that classes need for printing, copying, comparing and so on. OVM allows you to specify the automation needed for each field and to use a built-in, mature and consistent
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Low-Power Verification With SystemC - The Great Unknown
By
Team genIES
on
January 28, 2010
Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models
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Changing The "F" in RTFM to "Fantastic"
By
Team genIES
on
January 12, 2010
Talk about unsung -- tech writers just don't get the credit they deserve. They sit between R&D, customers, and support trying to capture the capabilities and intent of the software and present it accurately and succintly. They record the "
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AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance
By
Team genIES
on
January 8, 2010
The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders
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Are You Playing with a Full Deck?
By
Team genIES
on
December 15, 2009
A professional gambler confidently place bets because she know the odds, but she would be crazy to play at a table that didn’t use a full deck because the odds change in an unknown way. If you use a simulator that doesn’t enable low-power
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OVM Tricks and Treats
By
Team genIES
on
October 30, 2009
Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge
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Incisive Enterprise Simulator: Low-Power Verification at Warp Speed
By
Team genIES
on
September 9, 2009
Since your circuit always runs at low-power, your verification should too. To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively. In some cases that can result in tests
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FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364
By
Team genIES
on
July 23, 2009
The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today. Such a simple concept – I’m in a known state and I will either remain here or move to a new
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