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Blogger

Team FED

Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:

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How-to Plans for ECOs - Advice From Experts
By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or   Read More »
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Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs   Read More »
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Do You Also Need to be a DFT, STA, Verification, Low-Power, and Library Expert? Not Anymore!
By Jack Marshall Sr. Tech Leader, Solutions Our R&D team has just released a major new feature in RTL Compiler 9.1.100. It is called "Quality Analyzer". I call it "RC QA" for short - since that's how you invoke the feature   Read More »
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RTL Compiler's New "Spatial Technology"
By Jeff Flieder Sr. Solutions Manager Over the last few years, RTL Compiler has added a significant number of features targeted toward users that require more physical awareness in their synthesis flow. We first introduced the PLE (Physical Layout Estimation   Read More »
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DesignWare and AmbitWare Demystified - Why and When to Avoid?
By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have   Read More »
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RC Design Explorer: Find the Right Balance of Power and Performance
By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them. Lowering voltage levels can be a great way to reduce switching power, but   Read More »
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How to Pick a Synthesis Tool - The Right One for You - Part 2
By Kenneth Chang, Core Comp AE, Team FED . In my previous blog , I had written about how "Synthesis matters." Snippet below. <snip> I had a boss that once said that all synthesis tools are same. This guy knew his stuff, been in the industry   Read More »
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Free Online Training: Conformal LEC
By Kenneth Chang Core Comp AE Team FED . If you didn't know, Conformal's very own AE team put together some cool training materials for their customers based on large demand to help both new and intermediate users. It's free. And it's   Read More »
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Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate
By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not   Read More »
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Low Power Guide from Industry Leaders
By Kenneth Chang, Core Comp AE, Frontend Solutions. Low power concerns continue to drive companies' needs for optimized ASIC methodologies, which is why one of the Si2 key initiatives continues to be the standardization of Low Power Intent. Below   Read More »
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