Quiet Before The Storm? And What to Expect at DVCon 2010
By
Steve Svoboda
on
February 22, 2010
In the last couple weeks Mentor did an about-face and decided to embrace SystemC ( I told you that would happen! ), and then Synopsys threw down the gauntlet and decided to buy two Virtual Protoyping companies. Supposedly, the word on the street is they
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We and Our Competitors Agree (Well, Almost!)
By
Steve Svoboda
on
November 12, 2009
It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes Europe this week caught my eye, by Lauro Rizzatti the VP Mktg of EVE. Lauro discussed a survey EVE ran during DAC, where they asked customers how they felt about
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Keeping Trident Missiles "On Target" With System-Level Verification
By
Steve Svoboda
on
October 23, 2009
Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enough James Bond and Superman
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Synopsys’ “Synphony” Announcement – Welcome to the Party!
By
Steve Svoboda
on
October 14, 2009
I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity
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Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!
By
Steve Svoboda
on
October 3, 2009
Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back
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Industry Standard SystemC is What Designers Want
By
Steve Svoboda
on
July 3, 2009
This past Monday saw not one HLS related announcement but two...this space is really heating-up! Mentor’s Catapult announced support for control-logic design, and clock-gating (to reduce power) and Forte announced a new release with some minor new
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Synthesis Really DOES Need to Change
By
Steve Svoboda
on
June 2, 2009
A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “ Synthesis Needs to Change to Serve Modern Chip Design ”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful
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System-level Low Power Techtorials/Workshops Off To A Great Start!
By
Steve Svoboda
on
April 20, 2009
Back in my 24 March blog I mentioned how Cadence was kicking off a major techtorial/workshop series across North America on low power chip design, using the newest Cadence tools at the ESL/System/Chip Architecture level. Last week we concluded the first
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The Cadence ESL Machine Keeps Building Momentum!
By
Steve Svoboda
on
April 17, 2009
Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon Compiler (a finalist) received two write-ups in www.deepchip.com . One of the write-ups is by Gernot Koch of Micronas who evaluated CtoS last fall. I checked with
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Moving Low Power Chip Design up to the System Level
By
Steve Svoboda
on
March 24, 2009
Anybody watching Cadence these past couple years has probably noticed how we're pretty serious about investing in making tools for low-power design. While most of the attention in the EDA industry up to now has been on how to optimize chip power consumption
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