Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in 10 minutes, Now What?
By
Rama Jupalli
on
July 29, 2011
In my previous blogs , I talked about productivity enhancing features of Virtuoso Analog Design Environment XL and how designers can take advantage of these capabilities to design complex custom analog ICs. The Virtuoso Analog Design Environment XL multi
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Virtuoso Analog Design Environment XL – Make Friends with Variation
By
Rama Jupalli
on
June 16, 2011
In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity , I wrote about Virtuoso Analog Design Environment XL's multi-test bench environment and how design teams can make use of this feature to increase productivity and use
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Virtuoso Analog Design Environment XL – Embrace the Productivity
By
Rama Jupalli
on
May 6, 2011
In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better , I wrote about the improvements in Open Access, SKILL and Virtuoso Schematic Editor in Virtuoso IC 6.1. In this blog, I am going to focus on Virtuoso Analog Design Environment
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Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better
By
Rama Jupalli
on
April 13, 2011
With the recent release of unified custom/analog flow that is based on the latest version of the Virtuoso IC 6.1.5 technologies (see Virtuoso IC 6.1.5 press release here ), it is time to revisit the strengths of Virtuoso IC 6.1 platform and find out how
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Early Analysis is Key – Parasitic-Aware Design
By
Rama Jupalli
on
March 16, 2011
Decreasing geometries and increasing design complexity are making the task of designing custom ICs very difficult (not that it was easy before). One of the main issues designers grapple with is the issue of parasitics and their effect on design specifications
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