DAC 2010 – A “Coming Out” Party For 3D-IC Design
By
Rahul Deokar
on
June 28, 2010
Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the
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EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D
By
Rahul Deokar
on
April 16, 2010
Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. This was my first visit and chance to rub shoulders
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ST Microelectronics – A Fountain-head of Design Innovations
By
Rahul Deokar
on
January 22, 2009
In my last blog, I asked all of you to send me your design innovations. Thanks for your over-whelming response…and keep the emails coming in. And what better way to start the New Year than to talk about ST Microelectronics and its innovations!
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It’s the Season of Giving – Send Me Your Design Innovations!
By
Rahul Deokar
on
December 19, 2008
In the last blog, I wrote about innovating your way out of recession with new designs that address new challenges/requirements in new ways…and how the new Encounter Digital Implementation System can help. To further assist you on that front, we
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Innovate Your Way Out of Recession With the New Encounter!
By
Rahul Deokar
on
December 3, 2008
It's official! The U.S. economy has been in a recession for the past year. And, the global credit crunch and economic recession has pulled the semiconductor industry down to the point of entering its eleventh recession. "I'm sorry it's
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Need for dynamic IR drop analysis at floor and power planning stages?
By
Rahul Deokar
on
September 8, 2008
Here is a question for all the power grid designers out there: Do you see the need to do quick early dynamic rail analysis during floor and power planning stages of our design? With introduction of the Cadence Encounter Power System today, Cadence First
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Statistical Timing Analysis - Has its time arrived?
By
Rahul Deokar
on
July 21, 2008
At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation
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