DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups
By
Prabal Bhattacharya
on
March 30, 2012
On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled
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M/S Technology on Tour Blog – Model Validation and Assertion Based Verification
By
Prabal Bhattacharya
on
June 28, 2011
In February 2011, I had the opportunity to meet a group of analog and mixed-signal design and verification engineers in Boston, Austin and Irvine as part of the Cadence Mixed-Signal Tech-on-Tour program . This was a revealing experience for me in many
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