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Brad Griffin

16+ years in the biz

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Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support
IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling   Read More »
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Come See TeamAllegro at DesignCon2010
A new year means another DesignCon and 2010 is an exciting year for the PCB and IC Packaging team at Cadence – sometimes known as TeamAllegro. This year you will find the Cadence booth at an ideal location in the center of the Exhibition floor.   Read More »
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APD and SiP Layout 16.3 - Virtual-ly Amazing
On December 2, the Cadence Allegro team went live with the Cadence Allegro and OrCAD 16.3 Virtual Conference (CAO16.3). This virtual first in EDA was an amazing success with hundreds of visitors, many of whom visited the SiP and IC Packaging booth. If   Read More »
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Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26 Webinar
Co-Design … some are trying to do it with spreadsheets … everyone is talking about it. But talk is cheap. Can you really optimize a package footprint and a chip I/O padring such that that package and PCB costs can be minimized? What if using   Read More »
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Power Issues? Manage Your IR Drop The "Advanced" Way
Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions. In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature   Read More »
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Everything You Want to Know About APD / SiP 16.2 - Bill Acito Webinar on March 18
(N ote: Click here to view Bill Acito's webinar.) If you caught Jerry GenPart 's blog in November on Advanced Plating Bar Checks and wondered what else is new in APD 16.2, you are in luck. On Wed, March 18, Bill Acito, Product Engineer, will review   Read More »
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Designing DDR3 Interfaces In a Constraint Driven Design Environment
If you’ve been wondering how to capture high speed memory interface design intent early in your design process and drive that through to final verification, the Allegro PCB team has a number of ways we can help. First, be sure to attend or watch   Read More »
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Allegro PCB SI at DesignCon
Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification. In addition to other demos in the booth, be sure to mark your calendars   Read More »
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Cadence SiP and IC Packaging at DesignCon
Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI. This integration not only supports signal integrity, but also there is new package power integrity technology. We will also   Read More »
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Need some stability in your Package Power?
It is not too late to sign up for the Package Power Integrity webinar that will be presented on 10/23 11:00 PDT. Click here to register. This webinar will give you a heads-up on new (SPB 16.2) features in the package / SiP SI tools that can be used to   Read More »
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