Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose
By
Kenneth Chang
on
November 27, 2012
Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via
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Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line
By
Kenneth Chang
on
February 7, 2011
Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments
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Wrapping Up 2009 With Some Reflections
By
Kenneth Chang
on
December 23, 2009
As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of
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I Need ASIC IP. Where Can I Find Information?
By
Kenneth Chang
on
August 7, 2009
By Kenneth Chang. The world's best IP ecosystem is ChipEstimate.com . That's what we're hearing every day from our customers. Second to none as a solution, ChipEstimate.com took DAC by storm, with its incredible line up of IP Talks! sessions
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SDC Best Practices: What to do With "-through" Constraints?
By
Kenneth Chang
on
April 28, 2009
One of my customer's last week asked a good question that has come up many times before when I was a designer too. Customer : When is using "-through" in my SDC timing constraints a bad thing? Any guidelines? Here was my response for those
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My Twitter Experiment - Just Follow Me
By
Kenneth Chang
on
March 24, 2009
"I didn't know that Conformal ECO-physical was released. When did that happen? Which version of LEC?" , said one of my customers said recently. I have a lot of customers who ask about the latest product information once in a while. I see
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Making the Right Decisions *Before* You Start Your Project
By
Kenneth Chang
on
March 23, 2009
Seems logical, but unfortunately, I run into customers today that grumble about their past experiences such as: "Gosh, I wish our chip wasn't so big. How did that happen?", says one ... "Our memory requirements grew and grew, out of
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Build ASICs With a Strong Ecosystem: A New Paradigm
By
Kenneth Chang
on
February 5, 2009
Building ASICs is a pretty much standard process - you may define your specification based on whatever constraints you have, pick your IPs if any, do a guess-timate of your entire chip so you can figure out the budget, then commit - plunk down the cash
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Levels of Logic Analysis - A Thing of the Past? What's the Trend?
By
Kenneth Chang
on
January 7, 2009
For years as a designer, levels of logic analysis was a staple in the ASIC flows I worked on. Especially the last company (before I joined Cadence), the ASIC vendor we worked with forced us to abide by their Levels of Logic analysis metric before moving
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Flash: Qi Wang - Cadence Low Power Architect Presenting @ VLSI Conference in India
By
Kenneth Chang
on
January 6, 2009
Just a short note for those who will be attending the exciting 22nd International conference on VLSI design in India . Don't miss Dr. Qi Wang of Cadence, Senior Architect, who co-authored a paper and is co-presenting at this event @ 9am ! Location
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