What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!
By
Gerald "Jerry" Grzenia
on
May 20, 2013
Just a very "quick read" on a new option for Quickplace this week. The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components
Read More »
Comments
(0)
|
 |
What's Good About AMS Data Precision Options? They’re in the 16.6 Release!
By
Gerald "Jerry" Grzenia
on
May 13, 2013
Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed
Read More »
Comments
(0)
|
|
|
What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!
By
Gerald "Jerry" Grzenia
on
May 6, 2013
Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS ( Capture ) product has a few new enhancements for Saving designs. Read on for more details ... Save In the Hierarchy viewer
Read More »
Comments
(0)
|
|
|
What's Good About ADW’s Design Migration? 16.6 has many new enhancements!
By
Gerald "Jerry" Grzenia
on
April 29, 2013
Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables: – Netassembler – Archiver – Purge – Packager It was also less robust with dependencies on external programs, and the
Read More »
Comments
(0)
|
|
|
What's Good About FSP’s Design Compare? Check Out 16.6!
By
Gerald "Jerry" Grzenia
on
April 18, 2013
The 16.6 Allegro FPGA System Planne r (FSP) product has an extremely helpful Design Compare capability. With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP
Read More »
Comments
(0)
|
|
|
What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6 Release!
By
Gerald "Jerry" Grzenia
on
April 16, 2013
The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types: • Schematics (.cpm) • Layout design (.brd, .sip, .mcm
Read More »
Comments
(0)
|
|
|
What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself in 16.6!
By
Gerald "Jerry" Grzenia
on
April 9, 2013
Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer
Read More »
Comments
(2)
|
|
|
What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements!
By
Gerald "Jerry" Grzenia
on
April 3, 2013
The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements: Grouping in Design Entry HDL (DEHDL) Allegro PCB Editor Enhancements Read on for more
Read More »
Comments
(0)
|
|
|
What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!
By
Gerald "Jerry" Grzenia
on
March 25, 2013
In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models. Read on for more details … Adding Vias Adding a via is easier
Read More »
Comments
(0)
|
|
|
What's Good About Allegro Package Designer (APD) Bond Wire "Text In?" You’ll Need the 16.6 Release to See!
By
Gerald "Jerry" Grzenia
on
March 19, 2013
Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for die and BGA (standard) components, as well as for importing of netlist updates. In certain design scenarios, particularly for leadframe package designs, it is also desirable
Read More »
Comments
(0)
|
|
View older posts
»
|