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Blogger

Jack Erickson

Currently helping to transition RTL design and verification to SystemC/TLM and C-to-Silicon Compiler high-level synthesis. Held numerous AE and marketing positions in the past at Cadence, covering simulation, RTL synthesis, physical synthesis, floorplanning, and equivalence checking.

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Recap of Another Successful Japan C-to-Silicon User Seminar
Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They host about two per year, and the meetings have been growing in size and content. The November session drew 44 customers, representing 13 companies. The content spanned   Read More »
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New Capabilities in the C-to-Silicon Compiler 2013 Releases
2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular. We saw our customers take on over 75 new projects using C-to-Silicon, much of that coming from expanded adoption within our existing customers. These designs spanned   Read More »
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High-Level Synthesis Now Spans the Datapath-Control Spectrum
When we talk to prospective high-level synthesis (HLS) customers, one of the slides we show is a pie chart that breaks down the types of production designs (that we are aware of) for which customers have used C-to-Silicon Compiler. The current snapshot   Read More »
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High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?
My most recent blog post mentioned how utilizing new algorithms together with high-level synthesis can continue to drive innovation in hardware design by balancing power consumption with performance improvements. A great example of this is what Fujitsu   Read More »
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Slow Winter or New Spring for Hardware Design?
If you're looking for an entertaining gonzo take on the history and current state of hardware design, I highly recommend "The Slow Winter" by James Mickens, the "Galactic Viceroy of Research Excellence" at Microsoft. The premise   Read More »
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Forte and Cadence at DAC: How to Deploy High-Level Synthesis
It's no secret that the transition to high-level synthesis (HLS) has historically gone more slowly than expected. There were a number of reasons for this - the early tools could not successfully synthesize control logic, they could not match the quality   Read More »
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Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A   Read More »
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Why are Cadence and Forte Presenting Together at DAC?
You may or may not have noticed that Cadence's DAC Theater schedule features an intriguing combination of presenters next Tuesday: Tuesday, June 04, 2013 Time Company Topic ... ... ... 11:30 AM Forte and Cadence How to Broadly Deploy SystemC High   Read More »
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The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing.   Read More »
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What to See at the DATE Conference: High-Level Synthesis
The DATE (Design Automation and Test in Europe) Conference is next week (March 18-22, 2013) in Grenoble, France. If you are lucky enough to be in Grenoble at this time of year, it will be worth it to check out Session 11.2 "High-Level Synthesis and   Read More »
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