Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow
By
Wei Tan
on
January 31, 2011
It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the
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How Much Power is My Chip Really Using?
By
Wei Tan
on
October 20, 2010
Today I'd like to dive into one of the topics I mentioned in my blog in August -- measuring chip power. This seems to be one of the questions I get from many people. How can a design team effectively measure power all throughout the design flow, with
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5 Tips to Help You Finish Your Low Power Design Tapeout On Time
By
Wei Tan
on
August 27, 2010
So you're about to start your first low power design. Or second, third, or fourth. As with many tapeouts, you know that with today's tight market windows, most likely the project will go off with a sprinting start (architectural planning), followed
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Using A Dual Flop Methodology for Dynamic Power Savings
By
Wei Tan
on
July 10, 2009
Imagine this scenario: Your chip is a low power design. You’ve used everything in the book – clock gating, multiple threshold optimization, power shutoff, multiple supply voltages etc. What else can you do to reduce power in your design? Or
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Flow? What Flow?
By
Wei Tan
on
July 2, 2009
For EDA software, it seems that it takes just as much effort to develop a methodology to use the software, as writing the tool itself. Ask any CAD group or design group that has to develop their own methodology and you can quickly gauge the many challenges
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WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication's Latest Innovation on WiMAX Devices
By
Wei Tan
on
April 27, 2009
Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was unthought of just 10 years ago: people working on laptops, accessing wireless internet at broadband speeds. I don't know about you, but to me, that is simply amazing
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